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Friday, April 3, 2020

skew, latency, uncertainty,jitter

This phenomenon in synchronous circuits. The Difference in arrival of clock at two consecutive pins of a sequential element.
fig: skew representation
Sources of skew:
  • Wire interconnect length
  • Capacitive loading mismatch
  • Material imperfections
  • Temperature variations
  • Differences in input capacitance on the clock inputs
Types of clock skew:
  • Positive skew: if the capture clock comes late than the launch clock.

  • Negative skew: if the capture clock comes early than the launch clock.

  • Zero skew: when the capture clock and launch clock arrives at the same time. (ideally, it is not possible)

  • Local skew: difference in arrival of clock at two consecutive pins of sequential element.it can be positive and negative local skew also.
  • Global skew: the difference between max insertion delay and the min insertion delay.it can be positive and negative local skew also.
max insertion delay: delay of the clock signal takes to propagate to the farthest leaf cell in the design.
min insertion delay: delay of the clock signal takes to propagate to the nearest leaf cell in the design.
  • Useful skew: if the clock is skewed intentionally to resolve setup violations.

The delay difference from the clock generation point to the clock endpoints.

There are two types of latency:

Source latency: Source latency is also called insertion delay. The delay from the clock source to the clock definition points. Source latency could represent either on-chip or off-chip latency.

Network latency: The delay from the clock definition points (create_clock) to the flip-flop clock pins.

The total clock latency at the clock in a flip flop is the sum of the source and network latencies.

Set_clock_latency 0.8 [get_clocks clk_name1] ----> network latency
Set_clock_latency 1.9 –source [get_clocks clk_name1] -------> source latency
Set_clock_latency 0.851 –source –min [get_clocks clk_name2] -----> min source latency
Set_clock_latency 1.322 –source –max [get_clocks clk_name2] ------> max source latency

One important distinction to observe between source and network latency is that once a clock tree is built for the design, the network latency can be ignored. However the source latency remains even after the clock tree is built.

The network latency is an estimate of the delay of the clock tree before clock tree synthesis. After clock tree synthesis, the total clock latency from the clock source to a clock in of a flip flop is the source latency plus actual delay of the clock tree from the clock definition point to the flip flop.

Clock Uncertainty: clock uncertainty is the difference between the arrivals of clocks at registers in one clock domain or between domains. it can be classified as static and dynamic clock uncertainties.

Timing Uncertainty of clock period is set by the command set_clock_uncertainty at the synthesis stage to reserve some part of the clock period for uncertain factors (like skew, jitter, OCV, CROSS TALK, MARGIN or any other pessimism) which will occur in PNR stage. The uncertainty can be used to model various factors that can reduce the clock period.

It can define for both setup and hold.
Set_clock_uncertainty –setup 0.2 [get_clocks clk_name1]
Set_clock_uncertainty –hold 0.05 [get_clocks clk_name1]

Clock uncertainty for setup effectively reduces the available clock period by the specified amount as shown in fig. and the clock uncertainty for hold is used as an additional margin that needs to be satisfied.

Pre CTS uncertainty = clock skew + jitter + margin
CTS uncertainty = jitter + margin

Static clock uncertainty: it does not vary or varies very slowly with time. Process variation induced clock uncertainty. An example of this is clock skew.

Sources of static clock uncertainty

  • Intentional and unintentional mismatch in design
  • On-chip variation (OCV)
  • Load variation at every stage in clock distribution
Dynamic clock uncertainty: it varies with time. Dynamic power supply induced delay variation and clock jitter is the example of this

Sources of dynamic clock uncertainty:

  • Voltage droop and dynamic voltage variations
  • Temperature variations
  • Clock generator jitter  
Jitter: Jitter is the short term variations of a signal with respect to its ideal position in time. It is the variation of the clock period from edge to edge.it can vary +/- jitter value. From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. This can be modeled by adding uncertainty regions around the rising and falling edge of the clock waveform.
Sources of jitter:
  • Internal circuitry of the PLL
  • Thermal noise in crystal oscillators
  • Transmitters and receivers of resonating devices
The first important point is that there are two phases in the design of when we are using a clock signal. In the first stage i.e. during RTL design, during synthesis and during placement the clock is ideal. The ideal clock has no distribution tree, it is directly connected at the same time to all flip flop clock pins.

The second phase comes when CTS inserts the clock buffer to build the clock tree into the design that carries the clock signal from the clock source pin to the all flip flops clock pins. After CTS is finished clock is called “propagated clock”.

Clock latency term we are using when the clock is in ideal mode. It is the delay that exists from the clock source to the clock pin of the flip flop. This delay is specified by the user (not a real value or measured value).

When the clock is in propagated mode the actual delay comes into the picture then this delay is called as insertion delay. Insertion delay is a real and measured delay path through a tree of buffers. Sometimes the clock latency is interpreted as a desired target value for insertion delay.

Clock uncertainty> in the ideal mode we assume the clock is arriving at all the flip flop at the same time but ideally, we did not get the clock at the same time, maybe the clock will arrive at different times at different clock pins of a flip flop so in ideal mode clock assume some uncertainty . for example a 1ns clock with 100 ps clock uncertainty means that next clock pulse will occur after 1ns±50ps (either + or -).

The question of why the clock does bit always arrive exactly after one clock?
The reasons are:
  1. The insertion delay to the launching flip flop’s clock pin is different than the insertion delay of capturing clock (like maybe capture clock is coming before then the launch clock or capture clock is coming after the launch clock  that difference is called skew)
  2. The clock period is not constant. Some clock cycles may are longer or shorter than others in a random fashion. This is called clock jitter.
  3. Even if the capture clock path and launch clock path are identical may be their path delays are different because different derate are applies on the path because the chip having different delay properties across the die due to process voltage and temperature variation i.e. called OCV (on-chip variation). This essentially increases the clock skew.

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