VLSI- Physical Design For Freshers

Learn physical design concepts in easy way and understand interview related question only for freshers

No posts with label Timing%20arcs%20and%20unateness. Show all posts

No posts with label Timing%20arcs%20and%20unateness. Show all posts

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Physical Design
Input for Physical Design
Sanity Checks
Floorplanning
Questions Related to Floorplanning,Physical Only Cells, & Inputs of Physical Design
Physical Only Cells
Questions Related To Physical Only Cells
Powerplanning
UPF & Special Cells Used For Power Planning
Interview Questions
Sources of Power dissipation in CMOS
Interview Questions Related To Power Planning
Placement
Interview Questions Related To Placement
Clock Tree Synthesis (Part-I)
Skew, Latency, Uncertainty & Jitter
Crosstalk & Useful Skew
Clock Buffer, Normal Buffer & Minumum Pulse Width Violation
Clock Tree Routing Algorithm
STA,DTA,Timing Arc, Unateness
Transmission Gate,D Latch, D Flip Flop ,Setup & Hold Time
Global Setup &Hold Time
GATE 2020 ECE Digital circuits questions
GATE 2019 ECE Digital circuits questions
GATE 2018 ECE Digital circuits questions
Setup & Hold Checks Defined in Library
Time Borrowing concept
Time stealing concept
Non Linear Delay Model (NLDM) in VLSI
Wire Load Model (WLM)
Standard Parasitic Extraction Format (SPEF)
OCV & CRPR
PVT (Process Voltage Temperature)

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Clock Tree Synthesis
Digital Circuits
floorplanning
GATE Questions
Interview questions
physical design
physical only cells
Placement
power planning
Sources of power dissipation
STA
what is floorplanning
What is Power Planning

SOURCES

NPTEL lectures
CMOS VLSI DESIGN BOOK by NEIL & David
IEEE journals
Wikipedia
Google

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