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Saturday, December 14, 2019

inputs for physical design

Name of Inputs
File format
Given by
.v (Verilog)
synthesis team
Synopsys Design Constraints (SDC)
.sdc(written in TCL)
synthesis team
Timing library/logical library
.lib(liberty  file)
Physical library 
.lef(layout exchange format)
Technology file 
TLU+(Table Look Up)

Description of all inputs 
Netlist : 
  • Textual description of circuits components (like logic gates, combinational circuits, sequential circuits), so netlist is a collection of gates.
  • It contains the logical connectivity of all the cells.
  • It can also be a collection of resistors, capacitors or transistors.
example of netlist:
            module and_gate(y,a,b);
            input a,b;
            output y;
            AND2 U1(.Y(y), .A(a), .B(b));

Synopsys Design Constraints(SDC) :
These are timing constraints and used to meet the timings.
constraints are :
  • create clock definition
  • generated clock definition
  • Virtual clock
  • input delay
  • output delay
  • max delay
  • min delay
  • max transition
  • max capacitance
  • max fanout
  • clock latency
  • clock uncertainty etc..
and clock exceptions are also present in SDC
  • Multicycle Path
  • False Path
  • Half Cycle Path
  • disable timing arcs
  • case analysis
will explain each constraints in detail in further posts......

Timing library/logical library (.lib):

  • It contains timing information of standard cells, soft macros, hard macros.
  • It contains Functionality information of standard cells and soft macros.
  • Timing information like cell delay setup, hold, recovery, removal are present.
  • Design rules like max tran, max cap, max fanout, min cap are present
  • Contain power information.
  • PVT corners are also present. for every PVT corner the timing of cells is different. hence for every PVT corner there is a .lib file present
cell delay is a function of input transition and output load and is calculated based on lookup tables.
cell delays are calculated by Nonlinear Delay Model(NLDM) and composite current source (CCS) models.
CCS(Composite current source)
NLDM (Non-Linear Delay Model)
It’s like Norton equivalent circuit
It’s like Thevenin's equivalent circuits
current source used for driver modeling
Voltage source used for driver modeling
It 20 variables to account input transition and output load
It has only 2 variables
CCS is more accurate
Less accurate

CCS file is 10x times larger than NLDM because of more numbers of variables
Smaller than CCS file
Runtime for CCS is more
Runtime is less
in .lib file following units are present,
  • time units
  • voltage unit
  • leakage power unit
  • capacitive load unit
  • slew rate
  • rise and fall time 
for each cell following attributes are present,
  • area of cell
  • leakage power
  • capacitance
  • rise and fall capacitance
  • for each pin direction and their capacitance
Lookup tables are defined for different parameters like cell delay, hold, setup, recovery, removal with different matrix
                              cell_fall (delay_template_6x6) {
                              index_1 (“0.015, 0.04, 0.08, 0.2, 0.4, 0.8”);
                              index_2 (“0.06, 0.18, 0.42, 0.6, 1.2, 1.8”);
                                    values ( \
                                             “0.0606, 0.0624, 0.0744, 0.0768, 0.09, 0.098”, \
                                              “0.1146, 0.1152, 0.1164, 0.1212, 0.1314, 0.1514”, \
                                              “0.201, 0.2004, 0.2052, 0.2058, 0.2148, 0.2168”, \
                                              “0.48, 0.4806, 0.4812, 0.4824, 0.4866, 0.4889”, \
                                              “0.9504, 0.9504, 0.9504, 0.951, 0.9534, 0.975” \
                                              “0.6804, 0.6820, 0.6836, 0.6851, 0.6874, 0.6895" \);
# index_1 represents input transition.
#index_2 represents output load i.e output net capacitance.
Ques: what would be the cell_fall time if input_net_transition is 0.08 and the output load is 0.6?
Ans: 0.2058
example of library:
                      cell(OR2_3) {
                            area : 6.00
                            pin (O) {
                                direction : output;
                                 timing () {
                                 related_pin : "A";
                                 rise_propagation() }
                                 function : "(A||B)";   #functionality
                                 min_cap: }

                            pin (A) {

                                direction: input;
                                cap: ;}

Physical Library(.lef) :
  • It contains physical information of standard cells, macros, pads.
  • Contain the name of the pin, pin location, pin layers, direction of pin(in, out,inout), uses of pin (Signal, Power, Ground) site row, height and width of the pin and cell.
  • Contain the height of standard cell placement rows.
  • Macros information like cell name, size, dimensions, layout,blockages and capacitance are defined.
  • Design rules, via definitions, metal layers and metal capacitances are defined.
  • For every technology the via and layer definition are different, so in physical library defined the type of layer(routing/master slice/overlap), width/pitch and spacing, direction, resistance, capacitance, and antenna factor are defined
  • Contain preferred routing Directions, minimum width of the resolution 
   example of lef:
                             layer M2
                             type routing
                              width 0.50;
                              end M2
                              layer via
                                type cut
                              end via
                              macro AND_1
                                    origin 0.000
                                    size 4.5 by 12
                                    symmetry x y;
                                    site core;
                               pin A 
                                   dir input;
                                    layer M2
lef contains two types of views
  1. CELL view: it is a full layout of the block and used at the time of tape out.
  2. FRAM view: this is an abstract view that has only the pins, metals, via and blockages that are used in Placement & Route stages. this makes sure that the interconnection between the pins can be routed automatically and the routing tool will not route over existing metal/via areas otherwise any shorts will come into the picture.
Technology File : 
  • Contain the number of metal layers and vias and their name and conventions.
  • Design rules for metal layers like the width of metal layer and spacing between two metal layers.
  • Metal layers resistance and capacitance as well as routing grid.
  • Unit, precision, color, and pattern of metal layer and via.
  • Maximum current density is also present in the tech file.
  • Contains ERC rules, Extraction rules, LVS rules.
  • Physical and electrical characteristics of each layer and via. 
  • It contains nwell,pwell, metal pitch.
tech file should be compatible with both physical & timing libraries
example of tech file:
                      /* specify units and unit values*/
                                  technology {
                                            operating conditions
                    /* define six basic color used to create display colors*/
                                     [ primary color {
                                                                } ]
                  /* define layer specific characteristics including display*/
                  /* characteristics and layer specific routing design rules*/
                  /* define layer and data types*/
                  /* defining vias used in the design */
                  /* define inter layer ruting design rules */
                  /* defining cell rows spacing rules */
                  /* defining density rules*/
                  /* defining via and slot rules*/
                  /* defining capacitance ,resistace and temperature coeff of the layer*/ 
TLU+(Table Lookup) :     
  • It is a table containing wire cap at diffrent net length and spacing.
  • contain RC coeficients for specific technology.
  • TLU+ files are extracted or generated from ITF(contains interconnect details) file results.
  • The main function of this files are--
              [a] . Extracted R, C parasitics of metal per unit length
              [b] . These RC parasitics are used for calculating net delays.
              [c].  If TLU+ files are not present these R,C parasitics extracted from.ITF files
              [d]. For loading of TLU+ we have to load 3 files: 1. TLU+ 2. Min TLU+ 3. Max TLU+ 
              [e]. Map file maps the .itf file and .tf files of the layer and via names.
Milkyway.tf also contain parasitics model of wire as TLU+ contains. If you specify in ICC the TLU+ files then ICC used TLU+ files and did not read parasitics from .tf. if not specified by default ICC will use .tf.
advantage of TLU+
1.more accurate
2.different TLU+ for different RC corners and scenario.
disadvantage of Milkyway.tf ---It used only for one RC corner.

Interview  Questions related to this topic:
  1. What are the inputs for physical design?
  2. What does lef and lib and .tf files contain?
  3. How the cell is defined in the library?
  4. What does sdc file contains?
  5. What is cell delay and net delay and how it is defined and calculated?
  6. What are different timing delays models available and what is WLM?
  7. From where do you get the WLM? Do you create WLM? How do u specify?

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