STA-II TRANSMISSION GATE,D LATCH, DFF,SETUP &HOLD

Before going to understand the setup and hold timing we should have to know about D latch and D FF and D latch and D FF is made up of transmission gate and inverters. So in this post, I will cover transmission gate, D LATCH, D FF,

setup up and hold time.

Transmission Gate:

The transmission gate is consists of a parallel connection of PMOS & NMOS.

Two gate voltage of PMOS and NMOS are the complement of each other.

The effective resistance of the transmission gate is almost constant because of the parallel connection of PMOS and NMOS.

It is a bidirectional circuit and it carries the current in either direction.

                     Transmission Gate

Truth table

NOTE: PMOS is on when gate input is 0.

               NMOS is on when gate input is 1.

Working: When control is high (1) from the truth table we can see both transistors are ON at the same time and whatever is applied to the input we got at the output.

When control is low (0) from the truth table we can see both transistors are OFF at the same time and whatever is applied to the input is not reached to the output so we got high impedance (Z) at the output.

D latch:

The latch is a level-sensitive device and it is transparent when the clock is high if it is a positive level-sensitive latch and when the clock is low it is called negative level-sensitive latch.

In latch the output (Q) is dependent only on the level of the clock (Clk). In this latch D is control the output (Q).

Positive triggered D latch waveform

Positive D latch using transmission Gate:

It consists of two transmission gates and two inverters.

When Clk = high (1) T1 is ON and T2 is OFF, so output (Q) directly follows the input (D).

When Clk = low (0) T1 is OFF and T2 is ON, now new data entering into the latch is stopped and we get only previously-stored data at the output.

Negative D latch using transmission Gate:

It is also consist of two transmission gate and two inverters. It is working in an exactly opposite manner of the positive level-sensitive D latch.

Negative triggered D latch waveform

When Clk = low (0) T1 is ON and T2 is OFF, so output (Q) directly follows the input (D).

When Clk = high (1) T1 is OFF and T2 is ON, now new data entering into the latch is stopped and we get only previously-stored data at the output.

D Flip flop:

A D flip flop is an edge-triggered device which means the output (Q) follows the input (D) only at the active edge (for positive rising edge) of the clock (for the positive edge-triggered) and retain the same value until the next rising edge i.e. output does not change between two rising edges, it should be changed only at the rising edge.

Positive edge-triggered D FF waveform

Negative edge-triggered D FF waveform

 D Flip flop using a transmission gate:

It is a combination of negative level-sensitive latch and positive level-sensitive latch that giving an edge-sensitive

device. Data is change only at the active edge of the clock.

Positive edge-triggered D FF using Transmission gate

when Clk= LOW (0) T1, T4 is ON and T2, T3 is OFF. 

New data (D) is continuously entering through T1 and getting

stored till the edge of T2 (path is D-1-2-3-4 and at node 4 it stops) it cannot pass through T2 and T3 transmission gate because they are off. This operation for the master latch. For slave latch it keeps retaining the previously stored value of output (Q) (path is 5-6-7-8-5).

when Clk is low 

When Clk= HIGH (1) T2, T3 are ON and T1, T4 are OFF.

              Now master latch did not allow new data to enter into the device because T1 is OFF and the previously stored data at point 4 is going through the path 4-1-2-5-6-Q and this same data is reflected at the output and this does not change until the next rising edge and this same data is also going to the transmission gate T4 (path is 4-1-2-5-6-7-8 and stops because transmission gate T4 is OFF).

when Clk is high

Again if Clk is low the master latching circuit is enabled and there is no change in the output. Any changes in input is reflected at node 4 which is reflected at the output at the next positive edge of the clock.

So we can say that if D changes, the changes would reflect only at node 4 when the clock is low and it will appear at the output only when the Clk is high.

Setup time:

The minimum time for which the data (D) should be stable at the input before the active edge of clock arrival.

The data is launched from FF1 and captured at the FF2 at the next clock edge. The launched data should be present at the D pin of capture flop at least setup time before the next active edge of the clock arrives.

So total time to propagate the data from launch to capture flop = one time period (T) –Tsu

This is the required time for the data travel from launch to capture flop.

And how much time it does take data to arrive at the D pin of capture flop is =Tcq (clock to Q delay of FF1) + Tcomb (combinational delay). This is called arrival time.

So condition for setup timing to not violate

RT > AT

Slack = RT –AT

Slack =+ve (no violation)

           =-ve (setup violation)

Now, what is Tsu (setup time)? How do we determine and how much should be the setup time of flip flop and from where we can find this.

Now, what is Tsu (setup time)? How do we determine and how much should be the setup time of flip flop and from where we can find this.

When the CLK is low the input (D) is following the path D-1-2-3-4 and it will take some time to reach at the node 4 that time we will call setup time.

What happens if data (D) is not stable for the setup time before the next active edge of the clock arrives?

So now when the clock turns high the data which has to be launched should be present at node 4 but since the data is slow it would not get enough time to travel till node 4 and the data (D) is still be present somewhere between node 2 and 3 (let's say) so we don’t know which data will be launched at the rising edge and output will be indeterminate because data is not reached at node 4 yet i.e. data is late.

If skew is present in the design:

The required time (RT) is = T – Tsu + Tskew

If there is a positive skew it means we are giving more time to data to arrive at D pin of capture FF. so positive skew is good for setup but bad for hold.

Tskew is positive or negative depending on the capture clock it comes fast or slow than the launch clock. 

Positive skew: if the capture clock comes late than the launch clock.

Negative skew: if the capture clock comes early than the launch clock.

for more information about skew follow the below link

https://www.physicaldesign4u.com/2020/04/skew-latency-uncertaintyjitter.html

Hold time:

The minimum time for which the data (D) should be stable at the input after the active edge of clock has arrived.

Data is launched from FF1 at 0sec and this data should be captured at FFF2 after one time period (T). The hold time is to make sure that the current data (n) which is being captured at the FF2 should not be corrupted by the next data (n+1) which has been launched from the launch flop at the same edge.

Why do we check to hold at the same edge itself?

Because this same edge is going to both the flip flops if at this edge The capturing flop FF2 is capturing the current data (n) at this same edge itself the launch flop FF1 is launching the next data (n+1) so the whole check is to make sure that this new data (n+1) which is being launched at the same edge from the launch flop FF1 should not come so fast that it corrupts the current data (n) which is being captured at the capture flop at the same edge.

The arrival time of this (n+1)^th data should at least be greater

than the Thold time of capture flop FF2. Basically this current data (n) should be held for enough time for it to be captured reliably, that enough time is called hold time.

                                           Arrival time         Required time

Hold slack = AT – RT

If hold slack = +ve (No violation)

                          = -ve (hold violation)

If arrival time is less that means data coming is very fast (or early) so hold violation occurs.

If positive skew is present:

It means the next data (n+1) will be launched early from the launch flop FF1 and till now the capture clock is not reached to the capture flop FF2 so the data (n) also did not have to capture yet, but this nth data has to be stable at the capture clock for Tskew+ Thold time otherwise data n will be corrupted. So we can say +ve skew is bad for hold.

Positive skew

If negative skew is present:

it means the data (n) is being captured at captured flop FF2 early but by the time (n+1) data will not be getting launched from the launched flop FF1, so the data (n) got enough time to be held at the input for it to be captured reliability but till now the launch flop did not launch (n+1) data. So negative skew is good for hold.

Negative skew

so the condition for hold time with skew,

Hold time (Thold) of flip flop:

For working of this structure please read DFF using the transmission gate.

The Clock is turning from low to high the T1 and T4 transmission gate is turned off and stop entering the new data (D) into the device but transmission gate T1 does not turn off the immediately it will take some time to become OFF because the clock (Clk) is passes through many buffer and inverter then reached to the transmission gate T1 so we can say that transmission gate also take some time to get turned OFF so during the time when it is turning OFF from ON during that time new data should not come and disturbed the current data which is being captured.

Basically new data should not enter into the devices during that time also so the hold time will be the time is to take the transmission gate to turn off completely after the clock edge has arrived.
if there is any combination delay in the data path then the hold requirement will change.

Sometimes we saw setup and hold time is negative in library file what is the significance of that? Can setup and hold time be negative?
https://www.physicaldesign4u.com/2020/04/sta-iii-global-setup-and-hold-time-can.html

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