**Digital Circuits Questions and Answers: GATE 2019 ECE (Electronics and Communication)**

**Ques1. In the circuit shown, what are the values of F for EN = 0 and EN =1, respectively.**

**A) 0 and D**

**B) Hi-z and D**

**C) 0 and 1**

**D) Hi-z and D’**

**sol:**Let’s consider the NAND gate output is x and this is the input for PMOS transistor and NOR gate output is y and this is the input for the NMOS transistor.

So x = (EN.D)’ and y = (EN’ + D)’

So there are two inputs EN and D
then 4 combinations are present. We all know that PMOS will conduct at logic 0
and NMOS will conduct at logic 1. The truth table is

From the truth table when EN=0,
both the transistors are OFF and not connected to ground and supply (VDD) so the
transistor is in high impedance state.

From the truth table when EN=1,
the output is equal to D value.

**Option (B)**

**Ques2. In the circuit shown, A & B are the inputs, and F is the output. What is the functionality of the circuit?**

**A) Latch**

**B) XNOR**

**C) SRAM Cell**

**D) XOR**

**Sol:**We all know that PMOS will conduct at logic 0 and NMOS will conduct at logic 1.

Here also two inputs A and B so 4
combinations of input will present.

Rearranging the circuit, for the ease of convenience.

The truth table is:

Rearranging the circuit, for the ease of convenience.

The truth table is:

**Case1: when A = 0, B = 0**

Both PMOS transistors are ON and
NMOS transistors are OFF so F is directly connected to the VDD. In this case output
is 1.

**Case2: when A = 0, B = 1**

Here, the transistor PMOS1 is OFF,
PMOS2 is ON, the transistor NMOS1 is ON and NMOS2 is OFF so from the figure we
can see that F is directly connected to the A and the value of A is 0 so F is
also 0.

**Case3: when A = 1, B = 0**

Here, the transistor PMOS1 is ON,
PMOS2 is OFF , the transistor NMOS1 is OFF and NMOS2 is ON so from the figure
we can see that F is directly connected to the B and the value of B is 0 so F
is also 0.

**Case4: when A = 1, B = 1**

Both PMOS transistor are OFF and Both
NMOS transistors are ON So F is directly connected to the AB and A & B
values are 1 and behave as AND gate so the output is 1

So from the truth table we
conclude that this is an XNOR gate truth table.

**Option (B)**

**Ques3. In the circuit shown, the clock frequency, i.e. the frequency of clk signal, is 12 kHz. The frequency of the signal at Q2 is …….kHz.**

**Sol:**from the fig.

D1 = Q1’Q2’

D2 = Q1

Q1 = D1

Q2 = D2

**State table:**

**NOTE: in MOD-N counter, if the applied frequency is “f” then output frequency is f/N.**

**“MOD N” indicates the number of states in the counting sequence.**

fout = fclk/3

= 12/3

**= 4 kHz**

**Ques4. The state transition diagram for the circuit shown is.**

Y = A’Q

_{n}’ + AQ_{n}…………. (i)
And D = (Q

_{n}Y)’…………. (ii)
Put Y value in equation (ii),

D = (Q

_{n}. (A’Q_{n}’ + AQ_{n}))’
On solving D = (AQ

_{n})’
And we know the next state
equation of D FF is Q

_{n+1 }= D
From the table, it is clear that
it is NAND gate so state diagram is:

When Q=0 and A=0 then it goes to
the Q=1

When Q=0 and A=1 then it goes to
the Q=1

When Q=1 and A=0 then it goes to
the Q=1 (same state)

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