## Friday, April 24, 2020

Global setup and hold time:
Sometime we saw setup and hold time is negative in library file what is the significance of that? Can setup and hold time be negative?

for understanding the working of D FF using transmission gate please read this post
https://www.physicaldesign4u.com/2020/04/sta-ii-transmission-gated-latch-dffsetup.html

Data path delay (Tcomb) = The Time taken for the data to reach at the input of transmission gate or D pin of FF.
Clock path delay (Tclkint) = The Time taken for the clock
to reach from clock generation point (clock) to the clk pin (clk) of transmission gate or Clk pin of FF.

Both setup and hold time are measured with respect to the active edge of the clock. For a pure flip flop (containing no extra gate delays) setup and hold time will always be a positive number and fixed once the chip is fabricated it can’t be changed. But if we put some glue logic around the FF data path and clock path then setup and hold requirement will be changed and we called this global setup time (Tsunew) and global hold time (Tholdnew) and these components are available as a part of the standard cell library.

Setup and hold time can be negative also depending on where we measure the setup and hold. If we want to measure setup and hold time at the component level then it may be negative.

First scenario: If some combinational logic is present between Data pin and transmission gate T1 (data path) or D input of flip flop.

For setup:
Some delay will be induced due to combo logic now the data will take more time to reach from D pin of FF to node 4. So we can say that setup time will be increased because of combo logic.
Set up time is the time, when data reach to node 4 and now combinational logic is present so the setup Time requirement will be increased.
Let us take delay of comb logic (Tcomb) is 1ns and the original setup time (Tsu) is 3ns.
Then new setup time (Tsunew) = Tsu + Tcomb
= 3ns +1 ns =4ns
Now data will take 4ns to reach at node 4.

NOTE: IF COMB DELAY IS PRESENT IN THE DATA PATH THEN THE SETUP REQUIREMENT IS INCREASED.

For hold:
There is some comb logic sitting between the Data input & transmission gate pin D so now what will happen during this time, the transmission gate T1 is turning OFF till clock is not high and the new data comes at the input of the FF it will have to travel through the comb logic delay before it goes inside and disturbed our original data which is being captured so can we say that if the delay is added in the data path our hold time will be decreased and new data have to wait until the new active edge of the clock will not arrive at the transmission gate T1.

Let us take original hold time of FF (Thold) is 2ns it means the clock takes 2ns to reach from the generation point (clock) to the clock pin (clk) of FF or transmission gate to turn off so during that time new data should not come into the device and data should be stable for 2ns at the input after the rising edge of the clock has arrived.
Then New hold time (Tholdnew) = Thold - Tcomb
= 2ns - 1 ns =1ns (positive hold time)

If Tcomb = 2ns
Tholdnew = Thold – Tcomb
= 2ns – 2ns = 0 ns (zero hold time)
If the comb logic is equal to internal clock delay then our hold time will be zero if hold time is zero it means no need to hold the data after the clock edge has arrived.

If Tcomb = 3ns
Tholdnew = Thold – Tcomb
= 2ns – 3ns = -1 ns (negative hold time)

Note: IF COMB DELAY IS PRESENT IN THE DATA PATH THEN THE HOLD REQUIREMENT IS DECREASED.

Summary:
If comb logic present between data pin to the D pin of flop then,

Tsunew = Tsu + Tcomb
Tholdnew = Thold – Tcomb

If Thold > Tcomb => Positive hold time
Thold < Tcomb => Negative hold time
Thold = Tcomb => Zero hold time

Second scenario: if clock delay is present in clock path (the clock is passed through some buffer and inverter to reach at the T1)

For setup:
It means the active edge of the clock will take more time to reach at the transmission gate from the clock generation point (clock) this is called internal clock delay. So what will happen if this delay is present?

So we know that as soon as the active edge of clock has arrived, the transmission gate T1 is turned off and it stops the data entering into the device. We also know that clock is not reaching to the T1 instantly because of the internal clock delay even though the active edge of clock arrived at the generation point and the transmission gate T1 is still ON and the data still have some time to enter into the device and reached at node 4, then we can say that if internal clock delay is present in the design, the setup requirement will be decreased because the data will get some extra time to enter into the device and stabilize at node 4 even though the clock has arrived at the reference point of the flip flop.

Let us take internal clock delay (Tclkint) is 2ns and Tsu is 3ns.
Then new setup time (Tsunew) = Tsu - Tclkint
= 3ns -2ns
= 1ns (positive setup time)

if internal clock delay (Tclkint) is 3ns,
Then new setup time (Tsunew) = Tsu - Tclkint
= 3ns - 3ns
= 0ns (zero setup time)

if internal clock delay (Tclkint) is 4ns
Then new setup time (Tsunew) = Tsu - Tclkint
= 3ns -4ns
= -1ns (negative setup time)

It means the data can reach 1ns later than the active edge of clock because internally clock will take more time to reach the transmission gate T1 and this data even though it arrives 1 ns late it will still be able to make it to node 4 and get stabilized.

For hold:
So we know that as soon as the active edge of clock has arrived, the transmission gate T1 is turned off and it stops the data entering into the device and data have to wait at the D pin of transmission gate T1 till the clock is going to low.
Then we can say that if internal clock delay is present in the design the hold requirement will be increased because the data will have to wait at the D pin of T1 to enter into the device
let take if internal clock delay (Tclkint) is 2ns and hold time (Thold) of FF is 2ns Then
New hold time (Tholdnew ) = Thold + Tclkint
= 2ns +2 ns =4ns

Summary:

Tholdnew = Thold + Tclkint
Tsunew = Tsu - Tclkint

If Tsu > Tclkint => Positive setup time
Tsu < Tclkint => Negative setup time
Tsu = Tclkint => Zero setup time

Third scenario: if some comb logic is sitting b/w Data pin and the D pin of FF and clock internal delay is present b/w clock generation point to the clk pin of FF.

New setup time (Tsunew) = Tsu +Tcomb - Tclkint
New hold time (Tholdnew) = Thold –Tcomb + Tclkint

more precise value:
when the chip is fabricating all the components on the chip have different propagation delay because of the PVT (process - voltage - temperature) conditions so Every cell has three types of delay max, min, and typical delay.

for setup we consider worst (max) data path and min clock path so,
New setup time (Tsunew) = Tsu +Tcomb(max) - Tclkint(min)

For hold we consider worst (max) clock path and max clock path so,
New hold time (Tholdnew) = Thold – Tcomb(min) + Tclkint(max)

Setup and hold values can not be negative simultaneously but individually they may be negative. so for the setup and hold checks to be consistent, the sum of setup and hold values should be positive.

from where got the setup and hold values: library file
so the next post is related to how the setup and hold are defined for rise and fall constraints in the library file (.lib).

1. Very helpfull to understand the concept

2. My all doubt clear regarding hold and set up time thank u

3. 4. 