## Sunday, May 3, 2020

Digital Circuits Questions and Answers: GATE 2020 ECE (Electronics and Communication)

some times the many product based or service companies directly asked the GATE question in the written exam, there 50% of the questions were from the Electronics main stream Bachelors courses like digital, electronics devices, analog electronics, network theory, etc. If you prepared for GATE; then you can score most of these questions. The rest of the questions were focused on aptitude.

Que1: P, Q, and R are the decimal integers corresponding to the 4-bit binary number 1100 considered in sign-magnitude (P), 1’s complement (Q) and 2’s complement (R) representation respectively. The 6 bit 2’s complement representation of (P+Q+R) is….
A) 110101
B) 110010
C) 111101
D) 111001

Sol: 4 bit binary number is 1100.
First bit (MSB) is represented as a sign and other remaining bits are magnitude for all representation like sign-magnitude, 1’s complement, and 2’s complement representation.
If the first bit (MSB) is 0 then the magnitude will positive and if a first bit (MSB) is 1 then magnitude will negative.
• For sign-magnitude representation:

 1 MSB 1 0 0 LSB
Sign bit                  magnitude bits

So the sign-magnitude representation (P) of 1100 is: -4
P= -4
• For 1’s complement representation:

 1 MSB 1 0 0 LSB

MSB bit take as it is because it is the sign bit and takes 1’s complement of remaining bits
1’s complement representation (Q) of 1100 is: 1 011 i.e. -3
Q = -3

• For 2’s complement representation:

MSB bit take as it is because it is the sign bit and takes 2’s complement of remaining bits
1’s complement representation of 1100 is: 1011 adding 1 into this number we get 2’s complement so the 2’s complement representation (R) of 1100 is: 1011+1 = 1100
R = -4

Then P+Q+R = -4 -3 -4 = -11

Now before we have to take its 2’s complement representation of 6 bit we have to convert this 11 into a binary number.

The binary representation of +11 is in 6 bit = 001011 (in starting take 2 zeros because in ques it is giving 6 bit)

The sign-magnitude representation of -11 is in 6 bit = 101011 (first bit is sign bit)

The 1’s complement representation of -11 is in 6 bit = 110100 (first bit is sign bit)

For finding the 2’s complement add 1 in the 1’s complement number.
The 2’s complement representation of -11 is in 6 bit = 110100 +1 = 110101 (first bit is sign bit).
So the answer is 110101 option (A).

Ques 2: In an 8085 microprocessor the number of addressee lines required to access a 16KB memory bank is …
Memory capacity depends upon the amount of data that can be stored. The memory size representation in terms of address lines and data, lines are given below.
Memory size = 2A x D
Where A = address lines and D = data lines
210 = Kil0
220 = Mega
240 = Giga
250 = Tera and so on.
16kb = 24 x 210 byte
= 214 x byte
And this is equivalent of 2A x D so we can say that 14 address lines are required.

Ques 3:  The figure below shows a multiplexer where S1 and S2 are the select lines, I0 to I3 are input data lines, EN is enabled line and F (P, Q, R) is the output. So F is ….
A) PQ + Q’R
B) P + QR’
C) PQ’R + P’Q
D) Q’ + PR

Sol: Mux is combinational circuits. here EN is EN’ and the value of EN’ = 0, And EN = 1, so this mux is in working condition.

The output equation for 4:1 mux is if enable is present:
F = EN’. (S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3)
F = 1 (P’Q’R + P’Q.0 + PQ’R + PQ.1)
F = P’Q’R + PQ’R + PQ
F = Q’R (P’ + 1) + PQ
F = Q’R + PQ                          : (P’ + 1) =1
OPTION (A)

Ques 4: A 10 bit D/A Converter is calibrated over the full range from 0 to 10 v. if the input to D/A Converter is 13A (in hexadecimal), the output (rounded off to three decimal place) is ….v

Sol: full-scale voltage is 10 v.
Input to D/ A converter = 13A in hexadecimal
The output of DAC is
Vo = Resolution x [decimal equivalent of digital input]
Resolution = full scale output / No. of steps
No. of steps = 2n – 1
Binary equivalent of input (13A) is =000100111010
And decimal equivalent of input is = 314
So V0 = (10 x 314) / 210 – 1
= 3140/1023
= 3.069 volt

Ques 5: The state diagram of the sequence detector is shown below, state S0 is the initial state of the sequence detector. If the output is 1 then
A) The sequence 01010 detected.
B) The sequence 01011 detected.
C) The sequence 01110 detected.
D) The sequence 01001 detected.

Sol:  sequence detector is a sequential circuit that is used to detect the particular sequence as soon as the output is going to be 1. It means the complete sequence is detected then only the output is going to be 1 if the sequence is not detected the output is zero.

At S0 stage:  There are two possibilities, when input is 1 then it stayed on S0 (same state) only and if the input is 0 then it is going to next state S1 and still, the output is 0. So 0 is detected here.

At S1 stage:  There is a two possibilities, when input is 0 then it stayed on S1 (same state) only and if the input is 1 then it is going to next state S2 and still, the output is 0. So 1 is detected here.

At S2 stage:  There are two possibilities when input is 1 then S2 goes to the S0 state (initial state) and what we detected previously it will go, the sequence again started and if the input is 0 then it is going to next state S3 and still, the output is 0. So 0 is detected here.

At S3 stage:  There are two possibilities when input is 0 then S3 goes to the S1 state and what we detected previously it will go the sequence again started from S1 and if the input is 1 then it is going to next state S4 and still, the output is 0. So 1 is detected here.

At S4 stage:  There are two possibilities, when input is 1 then S4 goes to the S0 state (initial state) and what we detected previously it will go the sequence again started from S0 (initial state) and if the input is 0 then it is going to state S3 and here we got the output is 1. So 0 is detected here.

So the sequence we detect here is: 01010 (option A)

Ques 6: For the component in the sequential circuit shown below, tpd is the propagation delay tsetup is the setup time and thold is the hold time. The maximum clock frequency (rounded off to the nearest integer) at which the given circuit can operate reliably, is …… MHz

Sol: we know the setup and hold time definition.

Setup time :
The minimum time for which the data (D) should be stable at the input before the active edge of clock arrival, that minimum time is called setup time. If the data is not stable before that minimum time the setup violation occurs and we will not get the correct output.

Hold time:
The minimum time for which the data (D) should be stable at the input after the active edge of the clock has arrived.

So here we have to find the time between two active edge of a clock or after how much time the next clock edge arrives and we get data reliably. Initially we assume the data we get is stable.

Here input (IN) is externally applied to the EXOR and NAND gate so it has 0 (zero) delay.

When the clock is applied to both flip flop, the FF2 gets output after 8ns (propagation delay of FF2) and this output is the input to the FF1 and the FF1 gets output after 3ns (propagation delay of FF1) and this output is the input to the EX-OR gate. The output of the XOR gate is available after 5ns (3+2). Now the output of the XOR gate is the input to the NAND gate so the output of the NAND gate available after 7ns (3+2+2). The NAND gate output is the input to the FF2 means at 7ns.

For FF1 the after the first clock edge is arriving, the data is available at 8ns and stable for 5ns time (setup time of FF1) till the next clock has arrived so the time between two active clock edge is 13ns (8+5) i.e. the data must be stable until the next clock edge arrives.

For FF2, after the first clock edge is arriving, the data is available at 7ns and stable for 4ns time (setup time of FF2) till the next clock has arrived so the time between two active clock edge is 11ns (7+4) i.e. the data must be stable until the next clock edge arrives.

So here are two times between two active edges of the clock for FF1 and FF2 is 13ns and 11ns respectively, but we will consider the maximum time i.e. 13ns because for 13ns both the flip flop will work properly and we get reliable and stable output. If we consider 11ns time between two active edges of the clock then FF2 will work properly but FF1 will not work properly and get unstable output so we consider the maximum time 13ns. so T should be greater or equal to the 13ns.

So T >= 13 ns
And f < = 1/13ns
<= 76.923 MHz
And fmax = 76.923 MHz

# Digital Circuits Questions and Answers