Learn physical design concepts in easy way and understand interview related question only for freshers

Tuesday, December 31, 2019

Questions related to physical only cells

Ques:what are Decap cells.when do you use Decap cells?

Ques:What are the advantage and disadvantages of Decap cells?
  1. stable voltage between power and ground when signal net switch
  2. reduce dynamic IR drop
  1. consume chip area as they are bigger in size.
  2. leakage power consumption
Ques: Why filler cells are used? why we need fill in decreasing order of filler cell size.
  • Special filler cells are required to obtain the final layout, because placed standard cells can have free spaces between them that need to be filled. These spaces are also multiple of technology pitch and therefore the filler cells widths are chosen accordingly.
  • If we do DRC check we can expect spacing violations like "NWELL minimum spacing is not met", this is the condition where we have to use filler cells for continuity of NWELL.
  • If we are placed continuous low width filler cells it forms wide metal and create metal slotting rule violation.
  • The CMP process also introduce undesired side effects like dielectric erosion and metal dishing.As the number of metal layers and the wafer size is increases, the need of planarity across wafer becomes more crucial.chemical mechanical planarization/polishing (CMP) is a process of smoothing surfaces with the combination of chemical and chemical process.
To avoid metal slot rule violation always insert fat filler cells then thin filler cells. for example use one 20 um pitch filler cell and one 10 um pitch filler cellls instead of using 6 "5um pitch filler cells to fill 30 um spacing.
Metal slotting is a manufaturing issue, some process have special rules requiring metal wires have wide slot(e.g> 10-40 um)  .slots are long slits , on the order of 3um wide ,in the wire runninhg parallel to the direction of current flow. they provide stress relief, help keep the wire in place and reduce the risk of electromigration failure. these design rules vary widely between manufacturers.
fig: slots in wide metal power bus
Ques: can I add spare cells instead of filler cells.so that we have many spare cells for ECO?
Ans : NO, because 
  1. more static power consumption of spare cells as compared to filler cells.
  2. spare cells are not available in all sizes.
but we can replace filler cells with spare cells with logic.

Ques: Can I use FILL1 cells where i can use FILL32/64?
Ans: No, because following problems will comes
  1. metal slotting
  2. metal dishing
  3. dielectric erosion
Ques: what is ESD(Electrostatic discharge)?
Ans:There is a growing interest in the effects of ESD on the performance of semiconductor integrated circuits (ICs) because of the impact ESD has on production yields and product quality. ESD problems are increasing in the electronics industry because of the trends toward higher speed and smaller device sizes. ESD is a major consideration in the design and manufacture of ICs.
Static charge is an unbalanced electrical charge at rest. Typically, it is created by insulator surfaces rubbing together or pulling apart. One surface gains electrons, while the other surface loses electrons. This results in an unbalanced electrical condition known as static charge. When a static charge moves from one surface to another, it becomes ESD. It can occur only when the voltage differential between the two surfaces is sufficiently high to break down the dielectric strength of the medium separating the two surfaces. When a static charge moves, it becomes a current that damages or destroys gate oxide, metallization, and junctions. 
ESD can occur in any one of four different ways: a charged body can touch an IC, a charged IC can touch a grounded surface, a charged machine can touch an IC, or an electrostatic field can induce a voltage across a dielectric sufficient to break it down. 


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  2. can I add well tap cells instead of filler cells.so that we have many well tap cells can you please explain ?