Time Borrowing concept in STA

Time borrowing in VLSI

Difference between latches and flip flop:

https://www.physicaldesign4u.com/2020/04/sta-ii-transmission-gated-latch-dffsetup.html

Flip flop (Register)	Latch
Edge triggered and synchronous device.	Level sensitive and asynchronous device.
Flip Flops are of two types depending upon the clock signal polarity i.e. positive edge-triggered and negative edge triggered.	Latches are two types depending upon enable signal polarity i.e. positive level latch and negative level latch
Flip Flop are made up of latches (-ve latch and +ve latch)	Latches are made up of logic gates.
FF changes its state only when the active edge of clock (either positive or negative depending on requirement) is triggered.	Latches are transparent that means when they are enabled, output changes immediately if input changes.
Flip Flop based design are complex to design because they have clock signal and in FF to maintain the clock skew is big problem.	Latch based designs are simpler to design (because not based not edge of clock) and have a small die size. Latch based design is more variation tolerant and we get a better yield than the flip flop based design
The operation of FF based design is slower as compare to latches based design due to clock signal.	The operation of latches is faster because latches don’t wait for the clock edges.
The power requirement is more because of the clock signal.	Power requirement is less

There are two types of storage sequential circuits are flip flop (registers) and latches.

Flip flop based system:

Data launches on one rising edge of the clock and must set up before the next rising edge of the clock.

If the combinational logic delay present between two Flip Flops is very large then arrives late at the capture flip flop and data may goes into metastability.

If the combinational logic delay present between two FF is less i.e. it arrives early, so time is wasted in this case.

Latch based system

Data can pass through latch while the latch is transparent. If there is a large delay comb logic is present in the design then it can borrow the time from the next cycle. So latch based designs are used, where we want the high performance of the design.

Time borrowing is applies only to latch based design and cycle stealing for flip flop based design.

Time borrowing concept in latches:

It is the property of latch, a path ending at a latch can borrow time from the next path in the pipeline such that the overall time of two paths remains the same. STA applies a concept of time borrowing for latch based designs.

Whatever data launched from Flip Flop1 at ons it should be reached to Flip Flop2 at next active edge i.e. 10ns (ideal case when setup hold time and skew and clock delay all are zero). If data reaches at Flip Flop2 after 10ns will not be able to capture the correct data. Similarly if we launched our data from Flip Flop2 at 10 ns then it should be reached Flip Flop3 at 20ns (next active clock edge) without any violation.

What if the combinational logic delay is large (greater than time period 10ns):

If comb delay is greater than 10 then Flip Flop2 did not capture the correct data because Data is reaching at Flip Flop2 after 12ns and 0ns to 12ns Flip Flop will check only one positive edge so here this is the problem of setup violation so to avoid this we can use latch between positive levels.

What is latch: whenever the clock is enabled/high the latch will work for a half period of time depending upon the polarity.
https://www.physicaldesign4u.com/2020/04/sta-ii-transmission-gated-latch-dffsetup.html

Now if the Flip Flop2 is replaced with a latch where the gate of the latch is driven by the same clock line. 

What is the benefit of using this latch?

But if data reaches at latch after 10ns then what will happen?

If it reaches to the latch input before 10ns, this data waits at the latch’s D pin. This is a similar case as if we are using FF in place of latch.

Let say data is coming after the 12ns so there is a problem if we are using flip flop but if we are using latch there is no problem because the latch is transparent from 10 to 15, and no problem to receive the data so we can receive our data by borrowing the time from the next cycle, this means latch provides the advantage over Flip flop of 2ns time. The maximum time we can borrow is 5ns from the latch. But this time is reduced for the latch to flip flop3 so Flip Flop3 must get the data at 20ns so the latch must send the data before 20ns.

So we are borrowing the time from latch because it is open for 10 to 15ns and also this time is reduced for the next logic.

Now let’s look at the path from Latch to FF3:

The data comes out of Latch at 12ns will sample at Flip Flop3 at the time 20ns. Thus the path from latch2 to Flip Flop3 gets only 8ns time.

In the circuit which had all the flops, the second path had 10ns time however in this circuit it gets 2ns less time.

So it should be noted that the path from Flip Flop1 to Flip Flop3 still there is total 20ns which is not changed only distribution of time is changed.

So we can say that in flip flop based design the combinational delay should not longer than the clock period except for some exceptions like multicycle path and false path in static timing analysis.

In latch based design has larger combinational delay can be compensated by a shorter combination delay path in logic states. So for high performance of circuit we mostly used latch based design.

In simple term-time borrowing is the technique in which a longer path takes to borrow the time from the next path of subsequent logic.

Time borrowing typically affects the setup since time borrowing is slowing the data arrival time i.e. data arrival time is more. It does not affect the hold time because in hold time data arrival time is more.

Time borrowing examples:

Example1: There are two flip flops and 2 combinational logics arranged between flip flops. The clock period is 5ns.

Setup violation present in this scenario, because data coming to FF1 after 7ns and clock period is only 5ns. If we increase the clock period more than 7ns then the timing can be met. But increasing the clock period affects the performance of the design.

This timing violation issue can be resolved with the same clock period 5ns using the timing borrowing concept. We can replace the flip flop1 with the positive sensitive latch. Latch opens at the same time like flip flop at 0ns. This latch is open from 0ns to 2.5ns.

Ideally data from path1 should have arrived at ons but it is not reached. Path 1 borrowed 2ns from the latch if the latch is not present there would have been timing violation at ons. Now o.5ns used by path2.

So path1 have an extra 2.5ns time to borrow from the next cycle. Since latch closes at 2.5ns there is no timing violation for path1 because path1 arrives 0.5ns before the latch is closed.

Output of latch is immediately available for comb path2. From the fig path2 start where path1 left off. Path 2 could have used up to 3ns (0.5ns from previous stage + 2.5ns of half clock period of current cycle) but the given delay for path2 is only 1ns.

Valid data is available for capture flip flop2 at 3ns since the rising edge of capture Flip flop2 happens at 5ns. FLIP FLOP2 has extra 2ns this is +ve slack.

Time borrowing from the next cycle and using slack from the previous cycle. Timing is met without changing the clock, but just by replacing flip flop to latch. Time borrowing is used only for latch based designs.

Example 2: There are four positive level-sensitive latches and 4 combination logic between latches. Latch1 and latch3 are controlled by CK1, latch2, and latch4 are controlled by CK2. The relationship between ck1 and ck2 is shown in fig.

For simplicity all four latches assumed to have 0ns propagation delay and 0ns setup and hold time.

 case1: Path1 delay = 6ns

              Path2 delay = 1ns

              Path3 delay = 8ns

              Path4 delay = 1ns

Latch1 is opened at point A of ck1 and Latch2 is opened at point B of ck2. Data from latch1 is available at latch2 at 6ns. Since latch2 is opened from 5ns to 10ns then path1 can able to borrow 1ns from the path2.

Similarly path3 has a delay of 8ns, borrowed 3ns from the next stage. In both cases where we borrowed the time from the next stage is not used fully because path2 and path4 has delay less than 5ns the half of the clock period.

Case2: Path1 delay = 6ns

              Path2 delay = 1ns

              Path3 delay = 2ns

              Path4 delay = 1ns

Path3 has a delay of 2ns which is less than the 5ns (half clock period) it means NO TIME BORROWING is required from the succeeding stage. This is the same case as if there had been a flip flop instead of a latch.

NOTE: flip flop in place of latch4 stops time borrowing that we have seen from latch1 to latch3 at launch edge of flip flop.

Case3:Path1 delay = 6ns

             Path2 delay = 7ns

             Path3 delay = 5ns

             Path4 delay = 3ns

In this case there is 100% time borrowing because path1, path2, and path3 delays are greater or equal than the 5ns (half clock period). Each stage is automatically borrow the time from the succeeding stages until we get the output.

If the circuit made up of 4 flip flop instead of 4 latches, the 4 stage flip flop based design would consume a total of 28ns time but if we are using latch the delay has been reduced to 20ns. This is the advantage of latches over flip flops.

Time stealing:
https://www.physicaldesign4u.com/2020/05/time-stealing-and-difference-between.html