**Wire Load Model (WLM)**

**How
do you estimate the parasitics (RC) of a net before placement and routing? **

Prior to the Routing stage, net parasitics and delays cannot be accurately determined we know only the fanout of net and the size of the block.

Before going for floorplanning or layout, wire load models (WLM)
can be used to calculate interconnect wiring delays (capacitance (C),
resistance (R)), and the area overhead (A) due to interconnect.

The wire load model is also used to estimate the length of a net-based
upon the number of its fanouts.

The wire load model depends upon the area of the block, and
designs with different areas may choose different wire load models.

The wire load model also maps the estimated length of the net into
the resistance, capacitance, and the corresponding area overhead due to
routing. The average wire length within a block increases as the block size is
increased.

Generally, a number of wire-load models are present in the Synopsys technology library, each representing a particular size block of the logic. These models define the capacitance, resistance, and area factor of the net.

Typically a wire load model selection is based upon the chip area of the block. However these WLM models can be modified or changed according to the user’s requirement by the designers.

Figure shows different areas (chip or block size), having different wire load models would typically be used in determining the parasitics (RC), so from the figure, it is clear that the smaller sized block has a smaller capacitance.

**Example of a wire load model**

The wire load model specifies slope and fanout_length for the logic under consideration along with Resistance, capacitance, and area overhead. The fanout_length attribute specifies the value of the wire length that is associated with the number of fanouts.

If any fan out number is not explicitly listed in the table, the interconnect length is obtained by using linear extrapolation and interpolation with the specified given slope.

**wire_load**
(“wlm_conservative”) {

**resistance**:
6.0; # resistance per unit length of the interconnect

**capacitance**: 1.2; #
capacitance per unit length of the interconnect

**area**: 0.07; #
area overhead per unit length of the interconnect.

**slope**: 0.5; #extrapolation
slope used for data points that are not specified in the fan-out length table.

**fanout_length** (1, 2.6);

**fanout_length** (2, 3.1);

**fanout_length** (3, 3.6);

**fanout_length **(4, 4.1);

**fanout_length** (6, 5.1);

**fanout_length** (7, 5.6);

}

fanout_length (2, 2.9) means that for output pin with fanout equal 2, the wire length will be 2.9. Then you need to multiply this wire length with capacitance and resistance to calculate RC values for all wires.

These wire load models are based on statistical info (average wire length among different designs) and doesn't requires cell placement info (so it is easy, faster method, but not very accurate) i.e. just a rough estimate of the load that can be caused by wires. Wire load model information will be in the liberty files (what we call .libs) provided by the foundry.

Some companies create Custom WLM. - Just to have more accurate WLM for their own designs. They did place (and route) of their design, collect info of all wires (fanout and length for each net), and generate average length per fanout. For example, Synopsys Jupiter has such capability.

**Example1: for fan out of 8**

Fanout 8 is not present in
the table then we used linear extrapolation to calculate the length of
interconnect, Resistance, capacitance, and area overhead.

**For extrapolation**

**Length** =
Length of Last fanout number given in the table + (The fanout number we want – Last fanout number in WLM) * Slope

**Capacitance** =
New calculated Length * Capacitance coefficient given in the table

**Resistance **= New
calculated Length * Resistance coefficient given in the table

**Area overhead due to
interconnect** = New calculated Length * Area coefficient given in the
table

So, Length = 5.6 + (8 - 7)
* 0.5 = 6.1 units

Capacitance = 6.1 * 1.2 = 7.32 units

Resistance = 6.1 * 6 = 36.6

Area overhead due to
interconnect = 6.1 * 0.07 = 0.427

**Example2: for fan out of 12**

Length = 5.6 + (12 - 7) *
0.5 = 8.1 units

Capacitance = 8.1 * 1.2 = 9.72 units

Resistance = 8.1 * 6 = 48.6 units

Area overhead due to interconnect = 8.1 * 0.07 = 0.567 units

**Example3: for fan out of 5**

Since it is between fanout numbers 4 and 6 so we calculate the length using linear interpolation and linear interpolation between the two nearest pairs is used to estimate any points that are not in the lookup table.

**For interpolation:**

**Length** = Average of fanout
lengths = (Net length at fanout 4 + Net length at fanout 6)/2

**Capacitance** = New
calculated Length * Capacitance coefficient given in the table

**Resistance **= New calculated
Length * Resistance coefficient given in the table

**Area overhead due to
interconnect** = New calculated Length * Area coefficient given in the table

Length = (4.1 +5.1)/2 =
4.6

Capacitance = 4.6 * 1.2 = 5.52 units

Resistance = 4.6 * 6 = 27.6units

Area overhead due to
interconnect = 4.6 * 0.07 = 0.322

The units for the length, resistance, capacitance, and area are as specified in the library.

**Wire load Models Types:**

Till now we saw that for a particular net we can estimate the RC values as per the WLM. If a net crosses a hierarchical boundary, then different wire load models can be applied to different parts of the net and these wire load modes are of three types:

Top

Enclosed

Segmented

**Top:**

In this mode, all the nets
within the hierarchy use the wire load model of the top-level, and if any wire
load models specified in lower-level blocks (sub-blocks) then we ignored that
WLM model. Only the top-level wire load model takes precedence over all the WLM
modes.

From the figure, the wlm_1
wire load model specified in block A1 is used over all the other wire load
models specified in blocks A2, A3, and A4.

**Enclosed:**

In this WLM mode, the wire
load model of the block that fully encompasses the net is used for the entire
net.

From the figure, the net
Net1 is included in block A2 and thus the wire load model of block A2,
wlm_2 is used for this net.

Other net that is fully
contained in block A3 use the wlm_3 wire load model, and net that is fully
contained within block A4 use the wlm_4 wire load model.

**Segmented:**

In this WLM mode each
segment of the net gets its wire load model from the block that encompasses the
net segment. Each portion of the net uses the appropriate wire load model
within that block.

Figure illustrates an
example of a net Net1 that has segments in three blocks. The interconnect
within block, A3 uses the wire load model wlm_3, the segment of the net within
block A4 uses the wire load model wlm_4, and the segment within block A2 uses
the wire load model wlm_2.

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