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Wednesday, May 27, 2020

Standard Parasitic Extraction Format (SPEF)

Standard Parasitic Extraction Format (SPEF)


SPEF allows the representation of parasitic information of a design(R, L, and C) in an ASCII (American Standard Code for Information Interchange exchange format). A user can read and check the values in a SPEF file. Users would never create this file manually it is automatically generated by the tool. It is mainly used to pass parasitic information from one tool to another.


Interconnect parasitics depends on the process. SPEF supports the specification of all the cases like best-case, typical, and worst-case values. These triplets (best, typical, and worst) are allowed for R, L, and C values, ports slows, and loads. The units of the parasitics R, C, and inductance L are specified at the beginning of the SPEF file.


The figure shows that SPEF can be generated by place-and-route tool or a parasitic extraction tool, and then this SPEF is used by timing analysis tool for checking the timing, in-circuit simulation or to perform crosstalk analysis.

Parasitics can be represented at many different levels. SPEF supports three models.


Distributed net model: In this model (D_NET), each segment of a net route has its own R and C values.

distributed net model


Reduced net model: In this model (R_NET), on the load pins of the net have single reduced R and C, and on the driver pin of the net a pie model (C-R-C) is considered.


Lumped capacitance model: In this model, only a single capacitance is specified for the entire net.


Parasitics extracted from a layout can be defined in three formats:

Detailed Standard Parasitic Format (DSPF)

Reduced Standard Parasitic Format (RSPF)

Standard Parasitic Extraction Format (SPEF)


The SPEF is a compact format of the detailed parasitics. A SPEF file for a design can be split across multiple files and it can also be hierarchical. SPEF is the format of choice for representing the parasitics in a design due to its compactness and completeness


An example of a net with two fanouts (*I *8 and *I *10) is given below.

*D_NET NET_27 0.77181

*CONN

*I *8: Q O *L 0 *D CELL1

*I *10: I I*L 12.3

*CAP

1 *9:0 0.00372945

2 *9:1 0.0206066

3 *9:2 0.035503

4 *9:3 0.0186259

5 *9:4 0.0117878

6 *9:5 0.0189788

7 *9:6 0.0194256

8 *9:7 0.0122347

9 *9:8 0.00972101

10 *9:9 0.298681

11 *9:10 0.305738

12 *9:11 0.0167775

*RES

1 *9:0 *9:1 0.0327394

2 *9:1 *9:2 0.116926

3 *9:2 *9:3 0.119265

4 *9:4 *9:5 0.0122066

5 *9:5 *9:6 0.0122066

6 *9:6 *9:7 0.0122066

7 *9:8 *9:9 0.142205

8 *9:9 *9:10 3.85904

9 *9:10 *9:11 0.142205

10 *9:12 *9:2 1.33151

11 *9:13 *9:6 1.33151

12 *9:1 *9:9 1.33151

13 *9:5 *9:10 1.33151

14 *9:12 *8: Q 0

15 *9:13 *10: I 0

*END


CONTENTS in  SPEF FILE:


header_definition: contains basic information such as the SPEF version number, design name, and units for R, L and C.


[name_map]: specifies the mapping of net names and instance names to indices.


[power_definition]: declares the power nets and ground nets


[external_definition]: defines the ports of the design.


[define_definition]: identifies instances, whose SPEF is described in additional files


internal_definition: contains the guts of the file, which are the parasitics of the design.


HEADER DEFINITION


*SPEF "IEEE 1481-1999" ------------> SPEF version


*DESIGN "ddrphy1" ------------------> Design name


*DATE "Fri Sep 21 00:49:32 2005"---> Timestamp when the file was created


*VENDOR "SGP Design Automation_1"---> Vendor tool


*VERSION "V2000.09” ----> version number of the program that was used to generate the SPEF


*DESIGN_FLOW "PIN_CAP NONE" "NAME_SCOPE LOCAL" ---> specifies at what stage the SPEF file was created. It describes information about the SPEF file that cannot be derived by reading the file.


*DIVIDER / -----> specifies the hierarchy delimiter.


*DELIMITER: --> Delimiter between the pin and its instance.


*BUS_DELIMITER [ ] ---> specifies the prefix and suffix used to identify a bit of a bus.


*T_UNIT 1.00000 NS---> NS | PS: specifies the time unit


*C_UNIT 1.00000 FF----> PF | FF: specifies the capacitance unit


*R_UNIT 1.00000 OHM-----> OHM | KOHM: specifies the resistance unit.


*L_UNIT 1.00000 HENRY-----> HENRY | MH | UH: specifies the inductance unit.


 A comment in a SPEF file can be specified in two forms.

// Comment - until end of line.

/* This comment can be extended to multiple lines */


NAME MAP:

A name map consisting of a map of net names and instance names to indices, the SPEF file size is made effectively smaller, and more importantly, all long names appearing in only one place. It specifies the mapping of names to unique integer values (their indices).


 Format of Name Map:

*NAME_MAP

*positive_integer name

*positive_integer name

. . .

Example of Name Map

*NAME_MAP

 *1 memclk

*2 memclk_2x

*3 reset_

*4 refresh

*5 resync

*6 int_d_out[63]

*7 int_d_out[62]

*8 int_d_out[61]

*9 int_d_out[60]

*10 int_d_out[59]

*11 int_d_out[58]

*12 int_d_out[57]

 . . .

*364 mcdll_write_data/write19/d_out_2x_reg_19

*366 mcdll_write_data/write20/d_out_2x_reg_20

*368 mcdll_write_data/write21/d_out_2x_reg_21

 . . .

*14954 test_se_15_S0

*14955 wr_sdly_course_enc[0]_L0

*14956 wr_sdly_course_enc[0]_L0_1

*14957 wr_sdly_course_enc[0]_S0


This helps in reducing the file size by making all future references of the name by the index. A name can be an instance name or net name.


The name map thus avoids repeating long names and their paths by using their unique integer representation.


POWER DEFINITION SECTION:


Defines the power and ground nets.

*POWER_NETS VDDQ

*GROUND_NETS VSSQ


EXTERNAL DEFINITION SECTION:


It contains the definition of the physical & logical ports of the design.

Logical ports Format:

*PORTS

port_name direction {conn_attribute}

. . .

Example:

*PORTS

*1 I

 *2 I

*3 I

 *4 I

*5 I

*6 I

*7 I

*8 I

 *9 I

*10 I

*11 I

 . . .

*450 O

*451 O

*452 O

*453 O

*454 O

*455 O

*456 O


Here I is for input, O is for output and B is for bidirectional.


PHYSICAL PORTS

Format:

*PHYSICAL_PORTS

pport_name direction {conn_attribute}


DEFINE DEFINITION SECTION:


It defines entity instances that are referenced in the current SPEF.

*DEFINE instance_name {instance_name} entity_name

*PDEFINE physical_instance entity_name

*PDEFINE ---> Used when the entity instance is a physical partition instead of logical.

 example:

*DEFINE core/u1ddrphy core/u2ddrphy “ddrphy1”

This means that there would be another SPEF file with a *DESIGN value of ddrphy1 - this file would contain the parasitics for the design ddrphy1, and possible to have physical and logical hierarchy.


INTERNAL DEFINITION SECTION:


It describes the parasitics for the nets in the design. There are basically two forms:

  1. Distributed net, D_NET
  2. Reduced net, R_NET


Example of Distributed net parasitics for net *5426 (D_NET).


*D_NET *5426 0.899466

*CONN

*I *14212: D I *C 21.7150 79.2300

*I *14214: Q O *C21.495076.6000*DDFFQX1

*CAP 1

*5426:10278 *5290:8775 0.217446

2 *5426:10278 *16:3754 0.0105401

3 *5426:10278 *5266:9481 0.0278254

4 *5426:10278 *5116:9922 0.113918

5 *5426:10278 0.529736

*RES

1 *5426:10278 *14212: D 0.340000

2 *5426:10278 *5426:10142 0.916273

3 *5426:10142 *14214: Q 0.340000 *END


In the first line, *D_NET *5426 0.899466: *5426 is the net index and 0.899466 is the total capacitance value on the net.


The capacitance value is the sum of all capacitances on the net like cross-coupling capacitances that are assumed to be grounded, and load capacitances.


It may or may not include pin capacitances depending on the setting of PIN_CAP in the *DESIGN_FLOW definition.


In the second line is the connectivity section which describes the drivers and loads for the net. In:


*CONN


*I *14212: D I *C 21.7150 79.2300

*I *14214: Q O *C 21.4950 76.6000 *D DFFQX2

Where *I-----> internal pin

                *14212: D --> instance of D pin.

                *14212-->  index number

                 I ------->  load (input pin) on the net.

                 O ------> Driver (output pin) on the net.

                *C -----> coordinates of the pin

                *D-----> driving cell of the pin.


CAPACITANCE SECTION:


This section describes the capacitances of the distributed net.


1 *5426:10278 *5290:8775 0.217446

2 *5426:10278 *16:3754 0.0105401

3 *5426:10278 *5266:9481 0.0278254

4 *5426:10278 *5116:9922 0.113918

5 *5426:10278 0.529736


The first number is the capacitance identifier. In SPEF there are two forms of capacitance specification.


First through fourth are of one formà (first through fourth) specifies the cross-coupling capacitances between two nets. So in index 1 of capacitance is 0.217446 and it represents the cross-coupling capacitance between nets *5426 and*5290.


Fifth is of the second form à with index 5) specifies the capacitance to ground and in capacitance index 5, the capacitance to ground is 0.529736.

 

Notice that the first node name is necessarily the net name for the D_NET and here the name of D_NET is *5426. The positive integer 10278 in *5426:10278 specifies an internal node or junction point.


So capacitance index 4 states that there is a coupling capacitance between net *5426 with internal node 10278 and net *5116 with internal node 9922, and the value of this coupling capacitance is 0.113918.




RESISTANCE SECTION


Describes the resistances of the distributed net. 

*RES

1 *5426:10278 *14212: D 0.340000

2 *5426:10278 *5426:10142 0.916273

3 *5426:10142 *14214: Q 0.340000


The first field is the resistance identifier.

The first index is between the internal node *5426:10278 to the D pin on *14212 and the resistance value is 0.34.


The capacitance and resistance section can be better understood with the RC network shown pictorially in fig.


Second example of distributed net:

This net has two loads and one driver and the total capacitance on the net is 2.69358.


*D_NET*5423 2.69358

*CONN

*I *14207: D I *C 21.7450 94.3150 ------> load

*I *14205: D I *C 21.7450 90.4900------>load

*I *14211: Q O *C 21.4900 83.8800 *D DFFQX1-----------> driver

*CAP

1 *5423:10107 *547:12722 0.202686

2 *5423:10107 *5116:10594 0.104195

3 *5423:10107 *5233:9552 0.208867

4 *5423:10107 *5265:9483 0.0225810

5 *5423:10107 *267:9668 0.0443454

6 *5423:10107 *5314:7853 0.120589

7 *5423:10212 *2109:996 0.0293744

8 *5423:10212 *5187:7411 0.526945

9 *5423:14640 *6577:10075 0.126929

10 *5423:10213 1.30707

*RES

1 *5423:10107 *5423:10212 2.07195

2 *5423:10107 *5423:10106 0.340000

3 *5423:10212 *5423:10211 0.340000

4 *5423:10212 *5423:14640 1.17257

5 *5423:14640 *5423:10213 0.340000

6 *5423:10213 *14207: D 0.0806953

7 *5423:10211 *14205: D 0.210835

8 *5423:10106 *14211: Q 0.0932139

*END

Figure RC network for D_NET *5423 corresponds to the distributed net specification.



In general, an internal definition can comprise of the following specifications:

D_NET: Distributed RC network forms of a logical net

R_NET: Reduced RC network form of a logical net

D_PNET: Distributed form of a physical net

R_PNET: Reduced form of a physical net

*R_NET net_index total_cap [*V routing_confidence] [driver_reduction]

*D_PNET pnet_index total_cap [*V routing_confidence] [pconn_section] [pcap_section] [pres_section] [pinduc_section]

*END

*R_PNET pnet_index total_cap [*V routing_confidence] [pdriver_reduction]

*END


Here is the syntax.

*D_NET net_index total_cap [*V routing_confidence]

[conn_section]

[cap_section]

[res_section]

[inductance_section]

*END


INDUCTANCE SECTION

This section used to define the inductances and the format is very similar to the resistance section.


The *V is used to specify the accuracy of the parasitics of the net. The accuracy can be specified individually with a net and globally using the *DESIGN_FLOW statement with the ROUTING_CONFIDENCE value, such as:


*DESIGN_FLOW “ROUTING_CONFIDENCE 100” ---> means the parasitics were extracted after final cell placement and final route and 3d extraction was used.

The possible values of routing confidence are 10, 20, 30, 40, 50, 60, 70, 80, 90 and, 100.


REDUCED NET


It is the net that is the reduced from the distributed net. There is one driver reduction section for each driver on a net.  The example of a reduced net SPEF is below

*R_NET *1200 2.995

*DRIVER *1201: Q ----> DRIVER pin_name

*CELL SEDFFX1

*C2_R1_C1 0.511 2.922 0.106 ----> shows the parasitics for the pie model on the driver pin of the net

*LOADS *RC *1202: A 1.135

*RC *1203: A 0.946 --------> rc_value in the *RC construct is the Elmore delay (R*C)

*END

And the pictorial view of RC network is given below.



LUMPED CAPACITANCE MODEL:


It can be define using either a *D_NET or a *R_NET construct with only the total capacitance and no other information is given. The examples of lumped capacitance are given below.

*D_NET *1 80.2096

*CONN

*I *2: Y O *L 0 *D CLKMX2X3

*P *1 O *L 0 *END

*R_NET *17 58.5204

*END


Values in a SPEF file can be in a triplet form that represents the process variations, such as 0.243: 0.269: 0.300.

0.243 ----> best-case value

0.269 ----> typical value

0.300----> worst-case value.


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