Learn physical design concepts in easy way and understand interview related question only for freshers

Friday, January 3, 2020

Questions related to floorplanning,physical only cells, & inputs of physical design

Why we are following certain guidelines for macro placement and what are those guidelines?
Floorplanning is the most important stage in physical design. Quality of your chip implementation depands on how good id floorplan. A well oraganised floorplan results in more efficient utilization of the core area thereby aiding the placement of standard cells without causing issues related to congestion, timing, signal integrity etc.

if the floorplan is bad, it affects the area, power, reliability of the chip and requires more effort for closure and it can increase overall IC cost also. It can create all kind of issues in the design like congestion , timing, IR, routing issues. When placing large macros we must consider impacts on routing, timing and power.

  • Placement of macros are the based on the fly-lines ( its shows the connectivity b/w macro to macro and macro to pins) so we can minimize the interconnect length between IO pins and other cells.
  • Place the macros around to the boundary of core, left some space between macro to core edge so that during optimization this space will be used for buffer/inverter insertion and keeping large area for placement of standard cell during placement stage.
  • Macros that are communicating with pins/ports of core place them near to core boundary.
  • Place the macros of same hierarchy together.
  • Keep the sufficient channel between macros
  • channel width = (number of pins * pitch )/ number of layers either horizontal or  vertical 
  • Avoids notches while placing macros, if anywhere notches is present then use hard blockages in that area.
  • Avoid crisscross connection of macro placement.
  • Keep keep-out margin around the four sides of macros so no standard cells will not sit near to Macro pins. This technique avoids the congestion.
  • Keep placement blockages at the corners of macros.
  • For pin side of macros keep larger separation and for non-pin side we can abut the macros with their halo so that area will be save and Halo of two macros can abut so that no standard cell are placed in between macros.
  • Between two macros at least one pair of power straps (power and Ground) should be present.
  • Sensitive blocks (PLL,ADC,DAC ) should be placed far from high frequency blocks and high frequency IOs.
  • Macros alignment and orientation is correct and pins are on the edges

what is the minimum distance required in between macros if channel is there in non-pin side of macros?
Macro to macro spcing deciding factors are:
  1. Pin density
  2. Number of metal layers
  3. Routing pitch
channel width = (number of pins * pitch )/ number of layers either horizontal or  vertical 
Eg. Let’s assume If there is a two macros having 50 pins and the pitch values is 0.6 and the total number of horizontal and vertical layers are 12. Means M0 M2 M4 M6 M8 M10 are horizontal layers and M1 M3 M5 M7 M9 M11are vertical layers.
Channel width = ((50+50)*0.6)/6

= 10

what are the checks as you get netlist before going for floorplan?
  1. Netlist uniqueness
  2. Assignment statement
  3. Setup timing check
  4. SDC constraints (Clock frequency, uncertainty margins, exception path list (false path and multicycle path)
  1. Why we are following certain guidelines for macro placement and what are those guidelines?
  2. What is the minimum distance required in between macros if channel is there in non-pin side of macros?
  3. What are the checks as you get netlist before going for floorplan?
  4. What are pads and what do they do? How the IO pad arrangement will be done?
  5. What floorplan checks do you do to freeze?
  6. What are the floor planning steps?
  7. What is objective of floorplan?
  8.  What are Goals of floor planning?
  9. What are input and outputs for floor planning?
  10. What are the constraint you consider for floor planning of Macros and standard cells?
  11. What are Fence, Guide and region?
  12. What is Halo (Padding)?
  13. What are Placement blockages? Explain each.
  14. What are routing grids and manufacturing grid?
  15. What is the different between hierarchical design and flat design?
  16. What is the die size if standard cell area is 3 mm2 and macros area is 2 mm2?
  17. Could you place the standard cells in core to IO REGION?
  18. Why standard cell width is integer multiple of M2 pitch?
  19. How much placement density allowed at floorplan stage?
  20. What is floorplan and power plan?
  21. What are the steps to be taken care while doing floor planning?
  22. What is core and how will you decide W/H ratio for the core?
  23. What is effective utilization and chip utilization?
  24. How will you validate your floorplan?
  25. What are the steps involved in designing an optimal pad rings?
  26. What are the issues if floorplan is not good?
  27. How much aspect ratio should be kept?
  28. How will you decide pin location in block level design?
  29. Why do you use alternate routing approach HVH/VHV?
  30.  What is the distance between tap cells in design?
  31. What happens if you place macros at the center?
  32. How do you place macros in a full chip design?
  33. What are the parameter that differentiate chip design and block level design?
  34. What is the shape of your block?
  35. What is core and standard cell utilization?
  36. What are blockage explain each?
  37. Can you rotate the macros? 
  38. What is the difference between standard cell and macros? 
  39. What are fly lines?
  40. What kind of macros you had in the design?
  41. What will you do if you have congestion between macros?
  42. Your netlist area is grown much more than expected then what will you do?
  43. What are don’t use or don’t touch cells? Who will provide these cells?
  44. How the IO pad arrangement will be done?
  45. What are the different types of floor planning?
  46. If there are too many Pins of the logic cells in one place within the core, what kind of issue you face and how will you resolve.
  47. What are the issues if you see floorplan is bad?
  48. What are the standard cell rows?
  49. What is difference between soft macros and hard macros?
  50. What is partial floorplan?
  51. What are the challenges seen as technology shrinks.
  52. What are most challenging job in P&R
  53. Explain netlist to GDSII flow?
  54. What are the parameters you will consider while estimating die size?
  55. How to decide number of pads in chip level design?
  56. How do you use blockages techniques to reduce congestion?
  57. Why we need .lib floor planning?
  58. What is grid? Why we need and what are different types of grids?
  59. What are the steps involved in designing an optimal pad rings?
  60. How to decide number of pads in chip level?
  61. How to decide number of routing layers?
  62. How to decide full chip IO rings?
  63. How to decide total number of pins/pads and locations?
  64. How to decide design is pad limited or core limited?
  65. What is wire bond and flip chip packages?
  66. What is gridded and griddles routing?
  67. Explain top level pin placement flow? What are the parameters to decide?
  68. What is major advantage of using flip chip over wire bond package?
  69. What is need for sanity checks at floorplan stage?
  70. What are physical only cells?
  71. What corner cells contains?
  72. What is the difference between ore filler cells a metal filler cells?
  73. What are decap cells and what is the purpose of it? What are the advantage and disadvantages of Decap cells?
  74. Why filler cells are used? Why we need fill in decreasing order of filler cell size.
  75. Can I add spare cells instead of filler cells.so that we have many spare cells for ECO?
  76.  Can I use FILL1 cells where i can use FILL32/64?
  77. What is ESD (Electrostatic discharge)?
  78. Why endcaps cells are used and internal structure how to differentiate it with filler cells?
  79. What are tie high and tie low cells and where it is used?
  80. What are the inputs for physical design?
  81. What does lef and lib and .tf files contains?
  82. How the cell is defined in library?
  83. What does sdc file contains?
  84. What is cell delay and net delay and how it is defined and calculated?
  85. What are different timing delays models available and what is WLM?
  86. From where do you get the WLM? Do you create WLM? How do u specify?
  87. In which metal do you prefer the IO pins? How many metal layers (HVH) will you select for the below shaped blocks?

88.How much space/area do you take while doing floor planning if 8*32 bit bus talking from one macros to another macros?
89.Color region shows the routing congestion inside the chip? What is the reason?

If I get more questions, I will write here in the sequence...

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  1. Thank you for giving valuable information. I request you to make pages on synthesis stage with DC compiler and give information how to resolve the errors

  2. I want answers for that i mailed already.how can u contact with u.please send all answers to me