**What is Timing Analysis?**

We checked whether the circuit
meets all its timing requirements. The timing analysis is used to refer to
either of these two methods - static timing analysis, or the timing simulation
(dynamic timing analysis).

**What is static Timing Analysis?**

STA is the technique to verify
the timing of a digital design. The STA analysis is the static type and in this analysis of the
design is carried out statically and does not depend upon the data values being
applied at the input pins.

The more important aspect of
static timing analysis is that the entire design (typically specified in
hardware descriptive languages like VHDL or VERILOG) is analyzed once and the
required timing checks are performed for all possible timing paths and scenarios related to the design. Thus, STA is a complete and exhaustive method for verifying the
timing of a design.

In STA whole design is divided
into a set of timing paths having start and endpoints and calculate the
propagation delay for each path and check whether there is any violation in the
path and report it.

**What is Dynamic Timing Analysis?**

DTA is a simulation-based timing
analysis where a stimulus is applied on input signals, and resulting behavior
is observed and verified using the Verilog test bench, then time is advanced
with new input, the stimulus applied, and the new behavior is observed and
verified and so on. It is an approach used to verify the functionality as well as the timing of
the design.

This analysis can only verify the
portions of the design that get exercised by stimulus (vectors). Verification
through timing simulation is only as exhaustive as the test vectors used. To
simulate and verify all the timing paths and timing conditions of a design with
10-100 million gates are very slow and the timing cannot be verified
completely. Thus, it is very difficult to do exhaustive verification through
simulation.

**Why Static Timing Analysis?**

- STA is a complete and exhaustive verification of all timing checks of a design.
- STA provides a faster and simpler way of checking and analyzing all the timing paths in a design for any timing violations.
- Day by day the complexity of ASIC design is increasing, which may contain 10 to 100 million gates, the STA has become a necessity to exhaustively verify the timing of a design.

**Design flow for Static timing Analysis:**

In ASIC design, the static timing
analysis can be performed at many stages of the implementation. STA analysis
first done at RTL level and at this stage more important is to verify the
functionality of the design not timing.

Once the design is synthesized
from RTL to Gate – level, then STA analysis is used for verifying the timing of
the design. STA is also performing logic optimization to identify the
worst/critical timing paths. STA can be rerun after logic optimization to see
whether there are failing paths are still remaining that need to be optimized
or to identify the worst paths in the design.

At the start of physical design (PD) stages like floorplan and placement, the clock is considered as an ideal which means the delay from clock to all the sink pins of the flip flop is zero (i.e. clock is reaching to all the flip flop at the same time). After placement, in the CTS stage clock tree is built and STA can be performed to check the timing. During physical design, STA can be performed at each and every stage to identify the worst paths.

At the start of physical design (PD) stages like floorplan and placement, the clock is considered as an ideal which means the delay from clock to all the sink pins of the flip flop is zero (i.e. clock is reaching to all the flip flop at the same time). After placement, in the CTS stage clock tree is built and STA can be performed to check the timing. During physical design, STA can be performed at each and every stage to identify the worst paths.

In the logic design phase,
interconnect is ideal since there is no physical information related to the
placement of Macros and standard cells. In this stage, to estimate the length
of interconnect we used WLM (wire load model) which provides estimated RC
interconnect length based on the fan-out of the cell.

In the physical design stage, we
have the information about the placement of macros and standard cells and these
cells are connected by interconnect metal traces. The parasitic RC of the metal affects the delay and power dissipation in the design.

Before the routing is finalized
this phase is called the Global route phase, the implementation tool used to
estimate the routing length and the routing estimates are used to determine
resistance and capacitance parasitic that are needed to calculate the wire delays. Before the
routing stages we are not focused on the effect of coupling. After the detailed
routing complete, actual RC values obtained from the extraction tool (used to
extract the detailed parasitic from the design) and the effect of coupling also
analyzed.

**Limitations of STA:**- If all the flip-flops are in reset mode into their required values after applying synchronous or asynchronous rest this condition cannot be checked using static timing analysis.
- STA is dealing with only known values like logic-0 and logic 1 (or we can say low and high). If any unknown value X in the design comes then this value will not check by using STA.
- Ensure that correct clock synchronizer is present whenever there are asynchronous clock domain crossing is present in the design otherwise STA does not check if the correct clock synchronizer is being used.
- If the design having digital and analog blocks then the interface between these two blocks will not handle by STA because STA does not deal with analog blocks. Some verification methodologies are used to ensure the connectivity between these kinds of blocks.
- STA verifies the all the timing paths included that timing path also which does not meet all the requirements and even though logic may never be able to propagate through the path these timing paths are false paths. So we have to give proper timing constraints for false path and multicycle paths then only STA qor result will be better.

**Standard cells:**

Most of the complex functionality
in the chip is designed using basic blocks of AND, OR, NAND, NOR AOI, OAI cells
and flip flops. These blocks are predesigned and called standard cells.

The functionality and timing of
these standard cells are pre-characterized and available to the designer in the
form of standard cell libraries and use these blocks according to the
requirement.

**Propagation delay: https://www.physicaldesign4u.com/2020/03/cts-part-iii-clock-buffer-and-minimum.html**

**Transition (slew): https://www.physicaldesign4u.com/2020/03/cts-part-iii-clock-buffer-and-minimum.html**

**Timing arcs and unateness:**

**Timing arcs:**

The timing arc means a path from
each input to each output of the cell. Every combinational logic cell has
multiple timing arcs. Basically, it represents how much time one input takes to
reach up to output (eg. A to Y and B to Y). Like if we see AND, OR, NAND, and
NOR cell as shown in the figure. In sequential cells such as flip flop have
timing arcs from clock to the outputs and clock to data input.

Timing arcs can be further
divided into two categories – cell arcs and net arcs.

**Cell arcs:**This arc is between an input pin and an output pin of a cell i.e. source pin is an input pin of a cell and sink pin is the output pin of the same cell. Cell arcs can be further divided into sequential and combinational arcs.

**Combinational arcs**are between an input and output pin of a combinational cell or block.

**Sequential arcs**are between the clock pin and either input or output pin. Setup and hold timing arcs are between the input data pin and clock pin of flip flop and are termed as timing check arcs as they constrain a form of the timing relationship between a set of signals. Sequential delay arc is between clock pin and output Q pin of FF. An example of a sequential delay arc is clk to q is called delay arc and clk to D input is called timing check arcs in sequential circuits

**Net arcs:**These arcs are between driver (cell) pin of a net and load pin of a net i.e. the source pin is output pin of one cell and the sink pin is input pin of another cell. Net arcs are always a delay timing arcs.

**Unateness:**

Each timing arcs has a timing
sense that means how the output changes for different types of transitions on
input this is called unateness. Unateness is important for timing as it
specifies how the output is responding for the particular input and how much time
it will take.

**Timing arc unateness are of three types:**

**Positive unate:**If a rising transition on the input gives the output to rise and falling transition on the input gives the output to fall i.e. there is no change in transition of input and output then that timing arc is called positive unate.

Example: Buffer, AND, OR gate

**Buffer:**There are two-timing arc in buffer. First is rising input A to Y which gives rising output Y and second is for falling input A to Y that gives falling output Y i.e. what type of edge is giving to the input we got same at the output (output is constant).

**AND gate:**There are four timing arcs.

Input A to output Y for rising
edge

Input B to output Y for rising
edge

Input A to output Y for falling
edge

Input B to output Y for falling
edge

The truth table of AND gate is
shown in figure.

Check for

**rising edge,**from the truth table we can see that
If A = 0, and B (is going from 0
to 1): Y is constant at 0 (no change)

If A = 1, and B (is going from 0
to 1): Y is changed from 0 to 1

If B = 0, and A (is going from 0
to 1): Y is constant at 0 (no change)

If B = 1, and A (is going from 0
to 1): Y is changed from 0 to 1.

Check for the

**falling edge,**from the truth table we can see that
If A = 0, and B (is going from 1
to 0): Y is constant at 0 (no change)

If A = 1, and B (is going from 1
to 0): Y is changed from 1 to 0

If B = 0, and A (is going from 1
to 0): Y is constant at 0 (no change)

If B = 1, and A (is going from 1
to 0): Y is changed from 1 to 0.

**Negative unate:**If a rising transition on the input gives the output to fall and falling transition on the input gives the output to rise i.e. there is a change in transition of input and output then that timing arc is called negative unate.

Example: inverter, NAND, NOR gate

**Inverter:**There are two-timing arc in inverter. First is rising input A to Y which gives falling output Y and second is for falling input A to Y that gives rising output Y i.e. what type edge is giving to the input we got opposite of that at the output (output is inverted).

**NAND gate:**There are four timing arcs.

Input A to output Y for rising
edge

Input B to output Y for rising
edge

Input A to output Y for falling
edge

Input B to output Y for falling
edge

The truth table of NAND gate is
shown in figure.
Check for the

**rising edge**, from the truth table we can see that
If A = 0, and B (is going from 0
to 1): Y is constant at 1 (no change)

If A = 1, and B (is going from 0
to 1): Y is changed from 1 to 0

If B = 0, and A (is going from 0
to 1): Y is constant at 1 (no change)

If B = 1, and A (is going from 0
to 1): Y is changed from 1 to 0.

Check for the

**falling edge**, from the truth table we can see that
If A = 0, and B (is going from 1
to 0): Y is constant at 1 (no change)

If A = 1, and B (is going from 1
to 0): Y is changed from 0 to 1

If B = 0, and A (is going from 1
to 0): Y is constant at 1 (no change)

If B = 1, and A (is going from 1
to 0): Y is changed from 0 to 1.

**Non-unate:**The output transition cannot be determined by not only the direction of an input but also depends on the state of the other inputs.

Example: XOR, XNOR gate

**XOR gate:**There are four timing arcs.
Input A to output Y for rising
edge

Input B to output Y for rising
edge

Input A to output Y for falling
edge

Input B to output Y for falling
edge

The truth table of XOR gate is
shown in figure

Check for the rising edge, from
the truth table we can see that

If A = 0, and B (is going from 0
to 1): Y is changed from 0 to 1.

If A = 1, and B (is going from 0
to 1): Y is changed from 1 to 0 .

If B = 0, and A (is going from 0
to 1): Y is changed from 0 to 1.

If B = 1, and A (is going from 0
to 1): Y is changed from 1 to 0.

Check for the falling edge, from
the truth table we can see that

If A = 0, and B (is going from 1
to 0): Y is changed from 1 to 0 .

If A = 1, and B (is going from 1
to 0): Y is changed from 0 to 1 .

If B = 0, and A (is going from 1
to 0): Y is changed from 1 to 0.

If B = 1, and A (is going from 1 to 0): Y is changed from 0 to 1.

If B = 1, and A (is going from 1 to 0): Y is changed from 0 to 1.

**From where we can get timing arcs:**

We know that all the cell
information related to timing functionality is present in the library (.lib).
The cell is a function of the input to output. For all the combinations of
input and outputs and rising and falling conditions of inputs are defined in
the .lib file. In case you have to read SDF, this delay is picked from SDF
(Standard Delay Format) file. The net arcs taken from the parasitic values that
are given in SPEF (Standard Parasitic Exchange Format) file, or SDF.

nice work

ReplyDeleteGood information abt timing analysis, static and dynamic .

ReplyDeleteI have always read STA now got the good source to understand dynamic timing analysis too.

Grt workðŸ˜Š

Thanks ðŸ˜Š

DeleteGreat work. Worth it to me

ReplyDeletethanks sir

ReplyDeleteGood evening sir ,

ReplyDeleteInfo you gave us related to STA is worthy thanks for that

I have a query

How those analog and digital blocks will gonna interconnect and how the timing between those blocks will gonna optimise

Very nice compilation of all the resources at one place.

ReplyDeleteClear visibility of how the delay and arcs affect the timing analysis.

It was a gr8 experience reading this blog.

Excellent work..

ReplyDeletethank you sir for this valuable information

ReplyDelete