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Friday, January 17, 2020

interview questions related to power planning

Power planning related questions for interview:
  1. What are the challenge you will see in lower technology?
  2. What are the inputs and outputs from the power analysis?
  3. What are the checks after power planning is completed?
  4. What are the power dissipation components? How to reduce them
  5. Why float outputs are ignored but not float gates?
  6. How do you calculate the core ring width?
  7. What is IR drop? And how will you decrease this?
  8. What are general power margins?
  9. During power analysis, if you are facing IR drop problem, then how did you avoid that.
  10. What are the effects of IR drop?
  11. How IR drop affects setup and hold timing?
  12. Why high metal layers are preferred for VDD and VSS
  13. How to find number of power pads and IO power pads. How the width of metal and numbers of straps calculated for power and ground.
  14. What is power gating?
  15. CMOS power consumption details? Different types
  16. How you make sure that power structure is good?
  17. What is short circuit current and how will you overcome this problem?
  18. What is difference between static IR drop and dynamic IR drop?
  19. On what all parameter static IR drop and dynamic IR drop depends on?
  20. What is the purpose of static IR drop?
  21. How to reduce power/ground bounce?
  22. How you will fix EM violations. What are the step to minimize Electromigration?
  23. What is clock gating?
  24. Why is power planning done and how? Which metal should we use for power and ground rings & straps and why?
  25. What is the difference between level shifter and isolations cells?
  26. What is isolations cells and its types?
  27. How to find total power chip, what are the problems you can faced with respect to timing?
  28. How the numbers of power straps calculate.
  29. How did you do floorplanning?
  30. How to calculate core ring width, macro ring width and straps or trunk width?
  31. How do you reduce power dissipation using high VT and Low VT on your design?
  32. What are the various statistics available in IR drop reports?
  33. What is the importance of IR DROP analysis?
  34. What are low power techniques?
  35. What is the difference between footer switch and header switch in power gating?
  36. What is EM self-heating?
  37. How the cell modeled while power analysis?
  38. How core ring length matters while deciding the core ring width?
  39. After adding power straps if you have hot spot what to do?
  40. How to calculate core ring and straps width?
  41. How do you reduce standby (leakage) power?
  42. How to do power planning for multi voltage design?
  43. What is the tradeoff between dynamic power (current) and leakage power (current)?
  44. What are the power dissipation component? How to reduce them?
  45. What are the different reason for high voltage drop in the design?
  46. What is the need of UPF and what are the contents in UPF? Is always on cell present in UPF or not?
  47. If you have analog and digital (RAM) macros in your design how to do floorplanning?
  48. How many power domains are there in your project and how are they interlinked with each other?
  49. What is the issue if we see the design having current more than its defined capacity?
  50. How to reduce glitches power violations in the design?
  51. Explain power routing structure in your design?
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  1. Replies
    1. Will update soon ..after completion of all pd sta pv topics ..

  2. how and when will decaps are placed in design...?...how to decide if caps required in design?