Learn physical design concepts in easy way and understand interview related question only for freshers

Monday, January 13, 2020


Sources of power dissipation:
Power dissipation in CMOS circuits comes from two components:
Dynamic dissipation due to:
  • charging and discharging load capacitance as gate switch.
  • "short circuit" current while both PMOS and NMOS are partially ON.
         Pdynamic = Pswitching + Pshort circuit..........................................(1)

Static dissipation due to:
  • subthreshold leakage through OFF transistors
  • gate leakage through the gate dielectric
  • junction leakage from source /drain diffusions
         Pstatic = (Isub + Igate + Ijunction)Vdd.........................................(2)
         Ptotal = Pdynamic + Pstatic............................................................(3)

Dynamic power:
Whenever input signals in the circuit are changed its state with time, and it causes some power dissipation. Dynamic power is required to charging and discharging the load capacitance when transistor input switches
When the input switches from 1 to 0 the PMOS transistor (PULL UP network) turns ON and charges the load to VDD. And that time energy stored in the capacitance is
                      EC = ½ CL V2DD
The energy delivered from the power supply is
                         EC =  CL V2DD
Observed that only half of the energy from the power supply is stored in the capacitor. The other half is dissipated (converted to heat) in the PMOS transistor because transistor has a voltage across it at the same time current flows through it.  The dissipated power depends on only the load capacitance not on transistor or speed at which the gate switches.

When the input switches from 0 to 1, the PMOS transistor turns off and the NMOS transistor is turned ON, and discharging the capacitor. The energy stored in the capacitor is dissipated in the NMOS transistor. No energy is drawn from the power supply in this case.

Depending upon the inputs at the gate of the transistor one gate is on the other is off because of charging and discharging of the capacitor. The inverter is sized for equal rise and fall times so we know that in one cycle we have rising and falling transition.

On rising edge output change Q = CVDD is required to charge the output node to VDD (i.e. cap is charged to VDD) and on falling edge the load capacitance is discharged to GND.
Now suppose gate switches at some average frequency fsw (switching frequency). Over the time period T, the load is charging and discharging T*fsw times. So average power dissipation is
                    Pswitching = CV2DD fsw

This is called dynamic power because it arises from the switching of the load. Because most gates don’t switch every clock cycle, so it is convenient to express switching frequency as an activity factor(α) times the clock frequency f, now power dissipation written as
                       Pswitching = α CV2DD f
Activity factor:
The activity factor is the probability that the circuit node transitions from 0 to 1 because that is only the time the circuits consume power. A cock has an activity factor α = 1 because it rises and falls every cycle. The activity factor is powerful and easy to use lever for reducing power.
If a circuit can be turned off entirely, the activity factor and dynamic power go to zero. When a block is on the activity factor is 1. Glitches in the circuit can increase the activity factor.

Techniques to reduce dynamic power:
we know                   Pswitching = α C V2DD f
  • Reduce α (clock gating, sleep mode)
  • Reduce C (small transistors, short wires, smaller fan-out)
  • Reduce Vdd (reduce supply voltage up to which circuit works correctly)
  • Reduce f (reduce the frequency to the extent if possible power-down mode, without sacrificing the performance beyond acceptable level)
Short circuit power:
Dynamic power includes a short circuit power component. It occurs in CMOS when input of gate switches. When both pullup and pulldown networks are conducting for a small duration and there is a direct path b/w VDD to VSS. during this scenario spikes will be generated momentarily in the current as shown in fig below. The current is flowing from VDD to VSS is also called cross-bar current.
This is normally less than 10% of the whole power so it can be estimated by adding 10% to the switching power. This power is directly related to the frequency of switching, as clock frequency increases the frequency of transition is also increased thus short circuit power dissipation also increases. 
when both transistor are ON momentarily the short circuit comes in the form of spike
Clock gating:
Power dissipation is highly dependent on the signal transition activity in a circuit and the clock is mainly responsible for signal activities. Clock is the brain of the entire system so wherever clock transition takes place all the circuit works synchronously. Sometimes we have not required that clock to some blocks if we disable this clock to that particular block then switching activity reduced and activity factor α will also reduce and power dissipation also reduced.

The inactive Registers are loaded by clock not directly but loaded through the OR gate using enable signal. When we know we don’t require a functional unit we will set the enable to 1 so that the output of the OR gate will be constant 1, and the value of register will not change and therefore there will be no signal transition into a functional unit. When we are switching off the clock signal from the functional unit additional logic is required depending on the scenario that the functional unit required or not. But clock signal might add some delay in the critical path due to additional circuitry (OR gate and for enable different circuitry) then skew analysis is required.
We know in reality every gate has a finite amount of delay because of that delay only glitch will occur.
Let input A B C changes from 010 to 111.
When input 0 1 0 then output O1=1 and O2= 1
Now the input is changed to 111 then output O1 = 0 but O2 =1 remains the same. These both the ideal case when gate delays are zero.
Now what happened when we will consider the gate delays also?
The gate delay will be added on to both output because of the small amount of delay the glitch will appear.

so how it will be reduced?

The output is the same for both and the number of gates is also the same and we achieved reduced glitch power because the signal will reach at the same time in figure 2 (output of first and second gate) so there is no delay difference. Another advantage that the critical path delay is also reduced (in first figure it takes 3 gates to get the outputs and in second figure output takes only 2 gates. So we can reduce the glitch power dissipation by the realization of the circuit in balanced form instead of cascaded form.


We know two design approach

Static approach: where the distribution of power supply voltage is fixed a priori among various functional blocks.

Dynamic approach: where the power supply voltage is changed as required.

Static voltage reduction approach:
First, you analyze the circuit and we can reduce the supply voltage that will make your circuit consumes less power but the circuit becomes may be slower so you have to analyze the circuit and find out which part of the circuit is not critical in terms of delay, you can possibly make that part little slower without touching the overall performances. So identify those parts and reduce the power supply for that.
Suppose I have a circuit having three functional modules, let’s assume we required the central block to be running fast but the other two blocks are running slower. So we use pair of voltage rails one is for low supply voltage and the other is for high supply voltage so the block which is supposed to run faster they are fed by the high supply voltage and the other two feed by low supply voltages rails, so our voltage is saved.
Here the distribution of the voltages is always fixed and here additional circuitry is required between different power domains because signals are sending from slow block to fast block and vice versa, some voltage translation is required.

Dynamic approach:
We adjust the operating voltage and frequency dynamically to match the performance requirements.
The modern-day processors can have different power modes like our laptops have different mode standby, sleep, hibernate, etc. Previously power is not the issue now power becomes more important because everyone wants high-performance mode with high battery mode i.e. system should run for a longer time.
This approach provides flexibility & doesn’t limit the performance. The penalty of transition between two states can be high, it will take some time from one mode to another mode so it should not be done frequently.
High-performance mode: higher VDD and f
Power saving mode: lower VDD and f


Cells are arranged in a row, there are two different voltage domains high and low. So all the cells who are supposed to give the high performance will be placed in high voltage domain and lower performance cells are sits in the low voltage domain. This is allowed for both macros and standard cell voltage alignment. sometimes times voltage island is in the same circuit row like some circuit has performance and some have high but if we are doing this the problem of power routing will become more difficult.
Static power:
Static power is consumed even when a chip is not switching they leak a small amount of current. CMOS has replaced NMOS processes because contention current inherent to NMOS logic limited the number of transistors that could be integrated on one chip. Static CMOS gates have no contention current.
In processes with feature size above 180nm was typically insignificant except in very low power applications. In 90 and 65 nm processes, threshold voltage has reduced to the point that subthreshold leakage reaches levels of 1 sec to 10 sec of nA per transistor, which is significant when multiplied by millions of transistors on a chip.

In the 45 nm process, oxide thickness reduces to the point that gate leakage becomes comparable to subthreshold leakage unless high-k dielectric is employed. Overall, leakage has become an important design consideration in nanometer processes.
Static power sources:

  1. Subthreshold leakage current: b/w source and drain. This is the dominant source of static power
  2. Gate leakage current: from gate to body.
  3. Junction leakage current: from source to body and drain to the body.
Static power reduction techniques:

  1. Power gating
  2. Multiple threshold voltages
  3. Variable threshold voltages
Subthreshold leakage current:
It is caused by the thermal emission of carriers over the potential barrier set by a threshold. In a real transistor, current does not abruptly cut off below the threshold but rather drops off exponentially as shown in fig:
When the gate voltage is high (Vgs>Vt), the transistor is strongly ON. When the gate falls below Vt (Vgs < Vt) the exponential decline in current appears as a straight line. This current increase with temperature. It also increased as Vt is scaled-down along with the power supply for better performance.
Various mechanism affects the subthreshold leakage current

  1. DIBL effect
  2. Body effect
  3. Narrow width affect
  4. Effect of channel length
  5. Effect of temperature
Gate leakage current:
It is a quantum mechanical effect caused by tunneling through an extremely thin gate dielectric. Gate leakage occurs when carriers tunnel through a thin gate dielectric when a voltage is applied across the gate (when the gate is ON). Gate leakage is an extremely strong function of the dielectric thickness. Gate leakage also depends on the voltage across the gate. For gate oxides thinner than 15-20 Å, there is a nonzero probability that an electron in the gate will find itself on the wrong side of the oxide, and it will get away through the channel. This effect of carriers crossing a thin barrier is called tunneling and because of this leakage current is flowing through the gate to the body.
Two physical mechanism for gate tunneling are:

  1. Fowler- Nordheim tunneling: most important at high voltage and moderate oxide thickness
  2. Direct tunneling:  most important at lower voltage with thin oxides and it is the dominant leakage component.
Junction leakage current:
The p-n junction between diffusion and the substrate or well form diode as shown in fig: The well-to-substrate junction is another diode. The substrate and well are tied to GND or VDD to ensure these diodes do not become forward biased in normal operation. However, reversed – biased diode still conducts a small amount of current ID. Junction leakage occurs when a source or drain diffusion region is at a different potential from the substrate.
Static power reduction techniques:
The easier way to reduce static current during sleep mode is to turn off the power supply to the sleeping blocks. This technique is called power gating as shown in fig:
The logic block receives its power from a virtual VDD rail, VDDV.  When the block is active, the header switch transistors are ON and connecting VDDV to VDD.
When the block goes to sleep, the header switch turns OFF, allowing VDDV to float and gradually sink towards zero (0). As this occurs, the output of the block may take on voltage level in the forbidden or unknown state. The output of isolations gates forces the output to a valid level during sleep so that they do not cause problems in downstream logic.
Power gating introduces a number of design issues like header switch requires careful sizing, it should add minimal delay to the circuit during active operation and should have low leakage during sleep mode.
The transition between active and sleep modes takes some time and energy, so power gating is only effective when a block is turned off long enough. When a block is gated, the state must either saved or reset upon power-up. State retention registers use a second power supply to maintain the state. The important registers can be saved to memory so the entire block can be power-gated. The register must be reloaded from memory when power is restored.
Power gating was originally proposed as multiple threshold CMOS (MTCMOS) because it used low-vt transistors for logic and high-vt for header and footer switch.
Power gating can be done externally with disable input to a voltage regulator or internally with high–vt header and footer switches.  External power gating completely eliminates the leakage during sleep, nut it takes a long time and energy because the power network may have 100s of nF decoupling capacitance to discharge. On-chip power gating can use a PMOS header switch transistor or NMOS footer switch transistors. NMOS transistors deliver more current per unit width so they can be smaller.
On the other hand, if both internal and external power gating is used, it is more consistent for both methods to cut off VDD.
Power gating types:
  1. Fine –grained power gating
  2. Coarse-grained power gating

Fine-grained power gating: it is applied to individual logic gates, but placing this in every cell has enormous area overhead.

Coarse-grained power gating: in this the switch is shared across an entire block.


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