OCV (On Chip Variation) and CRPR (Clock Reconvergence Pessimism Removal)

What are OCV and CRPR?

How they are related?

CRPR (Clock Reconvergence Pessimism Removal) topic is comes after the STA introduces OCV (On Chip Variation) analysis, So here I  covered small introduction of OCV so that we can understand the CRPR and How CRPR is related to OCV.

we all know during the manufacturing of chips on the same die may suffer from variations due to process, voltage, or temperature change, thus transistors can be faster or slower in different dies.

Delays vary across a single die due to PVT (processor, voltage, temperature). The delay value of IC in cold weather is different and hot weather is different. In cold weather, the metals in IC will shrink so the delay will decrease. In hot weather, the metal will expand so the delay will increase.

The variation may be random or deterministic.  Random variations are oxide thickness variation, implant doses, and metal or dielectric thickness variations.

Suppose there is two inverters having the same characteristics on the single-chip but due to process, voltage, and temperature variation the delay of these two has different delay propagation.

To compensate these variations, STA introduces a concept called On-Chip Variation (OCV). In this concept, extra timing margins are added in timing analysis. In OCV, all cells or nets in the launch clock path, data path, and capture clock path will be added a fixed derate value, bringing more pessimism in timing analysis and compensating the variation.

In simple words, OCV is a technique in which this flat derate is applied to make a faster path more fast and slower path slower. so OCV adds some pessimism in the common path of lauch and capture path i.e. for a same cell there are two delays min and max.

In this concept, we remove the extra pessimism from common path. Generally, we add the delay to every buffer in the process of OCV. But adding more delay is also affects the speed of the chip and it may cause violations to overcome this we are removing the delay to the common path in the process of CRPR.

The delay difference along the common paths of the launching and capturing clock paths is called CRPR.

 

Problem: - In the fig three buffers, flip flops, combinational circuit have two delays one is min delay another is the delay after adding derating i.e. max delay. Consider Time period 8ns and Tsetup and Thold are 0.2ns.

Let's consider a buffer that is placed in a common path (both data path and clock path) for buf2 and buf3 buffer.

The tool calculates max. delays for setup calculation and min. delays for hold (worst- and best-case analysis). 

Without CRPR: -

Setup slack = (required time) min - (arrival time) max

Arrival time = 0.70 + 0.65 +0.60 + 3.6 = 5.55ns

Requited time = 8+ 0.60 + 0.45 -0.2 = 8.85ns

Setup slack = 8.85ns – 5.55ns = 3.3ns

Hold slack= = (arrival time) min - required time) max -

Arrival time = 0.60 +.55+.48+2.5 = 4.13ns

Requited time = .70 + .75+0.2 =1.65ns

Hold time = 4.13ns -1.65ns = 2.48ns

With CRPR:

When comes to OCV analysis, the tool further considers, max. for data path and min. for clock path during setup analysis. max. for clock path and min. for data path during hold analysis.

So, buffer placed in the common path now has 2 values i.e., max. and min. values. As we know, a cell can't have two different values at a particular instant of time. Thereby we calculate the buffer value as:

CRPR = Max. value - min. value

In the CRPR process we are removing the derating to common buffer. here the common buffer buf1.so we are considering 0.70ns-.60ns =.10ns for buf1.

Setup slack = (required time) min - (arrival time) max

Arrival time = 0.10 + 0.65 +0.60 + 3.6 = 4.95ns

Requited time = 8+0.10 + 0.45 -0.2 = 8.35ns

Setup slack = 8.35ns – 4.95ns = 3.4ns

Hold slack= = (arrival time) min - required time) max -

Arrival time = 0.10 +.55+.48+2.5 = 3.63ns

Requited time = .10 + .75+0.2 =1.05ns

Hold time = 3.63ns -1.05ns = 2.58ns

 

Without CRPR the setup and hold values are: - 3.3ns, 2.48ns

With CRPR the setup and hold values are: - 3.4ns, 2.58ns

From the above results, it is clear that with the CRPR method both setup and hold are benefited.

Some commands related to CRPR: 

pt_shell> set_operating_conditions -analysis_type on_chip_variation -min MIN -max MAX

pt_shell>set timing_remove_clock_reconvergence_pessimism TRUE

I will write about OCV (on chip variation) in some other post because this is a separate topic.