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Friday, February 28, 2020

CTS (PART- I)

CLOCK TREE SYNTHESIS (CTS)

Clock is not propagated before CTS so after clock tree build in CTS stage we consider hold timings and try to meet all hold violations.

After placement we have position of all standard cells and macros and in placement we have ideal clock (for simplicity we assume that we are dealing with a single clock for the whole design). At the placement optimization stage buffer insertion and gate sizing and any other optimization techniques are used only for data paths but in the clock path nothing we change.


CTS is the process of connecting the clocks to all clock pin of sequential circuits by using inverters/buffers in order to balance the skew and to minimize the insertion delay. All the clock pins are driven by a single clock source. Clock balancing is important for meeting all the design constraints.
fig: before the clock tree is not build
Checklist before CTS:
  • Before going to CTS it should meet the following requirements:
  • The clock source are identified with the create_clock or create_generated_clock commands.
  • The placement of standard cells and optimization is done. {NOTE: use check_legality –verbose command to verify that the placement is legalized. If cells are not legalize the qor is not good and it might have long run time during CTS stage}
  • Power ground nets- pre-routed
  • Congestion- acceptable
  • Timing – acceptable
  • Estimated max tran/cap – no violations
  • High fan-out nets such as scan enable, reset are synthesized with buffers.

Inputs required for CTS:
  • Placement def
  • Target latency and skew if specify (SDC)
  • Buffer or inverters for building the clock tree
  • The source of clock and all the sinks where the clock is going to feed (all sink pins).
  • Clock tree DRC (max Tran, max cap, max fan-out, max no. of buffer levels)
  • NDR (Nondefault routing) rules (because clock nets are more prone to cross-talk effect)
  • Routing metal layers used for clocks.

Output of CTS:
  • CTS def
  • Latency and skew report
  • Clock structure report
  • Timing Qor report

CTS target:
  • Skew
  • Insertion delay

CTS goal:
  • Max Tran
  • Max cap
  • Max fan-out
  • A buffer tree is built to balance the loads and minimize skew, there are levels of buffer in the clock tree between the clock source and clock sinks.

Effect of CTS:
Clock buffers are added congestion may increase non-clock cells may have been moved to less ideal locations can introduce timing and tran/cap violations.
fig: CTS structure after clock tree build
Checks after CTS:
  • In latency report check is skew is minimum? And insertion delay is balanced or not.
  • In qor report check is timing (especially HOLD) met, if not why?
  • In utilization report check Standard cell utilization is acceptable or not?
  • Check global route congestion?
  • Check placement legality of cells.
  • Check whether the timing violations are related to the constrained paths or not like not defining false paths, asynchronous paths, half-cycle paths, multi-cycle paths in the design.
Clock Endpoints types:
When deriving the clock tree, the tool identifies two types of clock endpoints:

Sink pins (balancing pins):
Sink pins are the clock endpoints that are used for delay balancing. The tool assign an insertion delay of zero to all sink pins and uses this delay during the delay balancing.
During CTS, the tool uses sink pins in calculations and optimizations for both design rule constraints for both design rule constraints and clock tree timing (skew & insertion delay).
Sink pins are:
A clock pin on a sequential cell
A clock pin on a macro cell

Ignore pins:
These are also clock endpoints that are excluded from clock tree timing calculations and optimizations. The tool uses ignore pins only in calculation and optimizations for design rule constraints.
During CTS the tool isolate ignore pins from the clock tree by inserting a guide buffer before the pin. Beyond the ignore pins the tool never performs skew or insertion delay optimization but it does perform design rule fixing.
Ignore pins are:
Source pins of clock trees in the fanout of another clock
Non clock inputs pins of sequential cells
Output ports

Float pins: it is like stop pins but delay on the clock pin, macro internal delay.


Exclude pins: CTS ignores the targets and only fix the clock tree DRC (CTS goals).

Nonstop pin: by these pin clock tree tracing the continuous against the default behavior. Clock which are traversed through divider clock sequential elements clock pins are considered as non-stop pins.

Why clock routes are given more priority than signal nets:
Clock is propagated after placement because the exact location of cells and modules are needed for the clock propagation for the estimation of accurate delay, skew and insertion delay. Clock is propagated before routing of signals nets and clock is the only signal nets switches frequently which act as sources for dynamic power dissipation.

CTS Optimization process:
  • By buffer sizing
  • Gate sizing
  • Buffer relocation
  • Level adjustment
  • HFN synthesis
  • Delay insertion
  • Fix max transition
  • Fix max capacitance
  • Reduce disturbances to other cells as much as possible.
  • Perform logical and placement optimization to all fix possible timing.
NOTE: MAINLY TRY TO IMPROVE SETUP SLACK IN PREPLACEMENT, INPLACEMENT AND POSTPLACEMENT OPTIMIZATION BEFORE CTS STAGES AND IN THESE STAGES NEGLECTING THE HOLD SLACK.
IN POST PLACEMENT OPTIMIZATION AFTER CTS STAGES THE HOLD SLACK IS IMPROVED. AS A RESULT OF CTS LOT OF BUFFERS ARE ADDED.

The below topics will discuss in the CTS II part...If any topic left in CTS please comment me then I will try to add in the second part of CTS 


difference between clock buffer and normal buffer?

what is pulse width violation?
what are the clock tree optimization process in detail?
what is useful skew and clock pushing and pulling in detail?
what is the difference between HFNS and CTS?
what are clock tree types?
what are the NDR rules applied to the clock net?
crosstalk noise and delay and it affects on set up and hold timing.
how positive skew is good for setup and negative skew is good for hold.
how to reduce the crosstalk effect.

email-id: physicaldesign4u@gmail.com

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10 comments:

  1. Thank you for your valuable time spending with us through this๐Ÿ˜Š

    Can you please make us topic for Generated clocks? Why generated clocks? Purpose of this? Is it affecting timing?

    ReplyDelete
  2. Yeah will update all SDC related topic in separate post ....thank you

    ReplyDelete
  3. And what is the difference between Skew and Uncertainty?
    As for above explanation both have same definitions. If so why can’t we call both are same?
    In case I am wrong please let me know.. thank you

    ReplyDelete
    Replies
    1. Skew and jitter are comes into the picture because of uncertainty ....
      During RTL synthesis some margin is giving to clock period that is called uncertainty ...have to gone through the NOTE part which I mentioned in red color ....

      Delete
  4. Replies
    1. Hi Anand ...now you understand ??

      Delete
    2. Yeah sir, Because of uncertainty only we are getting skew and jitter in non ideal clocks in CTS right?

      Delete
  5. what is difference between exclude pin and ignore pin

    ReplyDelete
  6. Good afternoon mam,
    please give information related to OCV (on chip variation) in CTS II

    ReplyDelete