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Saturday, December 14, 2019

What are the sanity checks before going to start physical design flow

Sanity checks:
To ensure that the input received from the library team and synthesis team is correct or not. If we are not doing these checks then it creates problems in later stages of design.
Basically, we are checking following input files: and make sure that these files are complete and not erroneous.
1.      design/netlist checks
2.      SDC checks
3.      Library checks
Design checks:
Check if current design is consistent or not
It checks the quality of netlist and identifies:
1.       Floating pins
2.       Multidriven nets 
3.       Undriven input ports
4.       Unloaded outputs
5.       Unconstrained pins 
6.       Pin mismatch counts between an instance and its reference
7.       Tristate buses with non-tristate drivers
8.       Wire loops across hierarchies
ICC command: check_design:
Checks for multi driven nets, floating nets/pins, empty modules.
Pins mismatch, cells or instances without I/O pins/ports etc. 

SDC Checks:
1.      If any unconstrained paths exist in the design then PNR tool will not optimize that path, so these checks are used to report unconstrained paths 
2.      Checks whether the clock is reaching to all the clock pin of the flip-flop.
3.      Check if multiple clock are driving same registers
4.      Check unconstrained endpoints 
5.      Port missing input/output delay.
6.      Port missing slew/load constraints.
ICC command: check_timing

Library checks:
It validate the library i.e. it checks the consistency between logical and physical libraries.
It checks the qualities of both libraries.
check_library: This command shows the name of the library, library type & its version, units of time, capacitance, leakage power, and current. It shows the number of cells missing, the number of metal or pins missing in the physical and logical library.

Ques: what checks you do as you get the netlist before going to the floorplan.?

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  1. thanks for your valueble information

  2. What we would if we have issues with multidriven nets floating input is there in design?

    1. Multidriven Nets: It means that cell pin is connected to nets but there is no driver to it. Which must be report to FE if such cases are present.
      Floating inputs port are must be a future use purpose so it must be tie it with low or high.

  3. what is diff between unconstrained endpoints and unconstrained paths

    1. Unconstrained paths : Unconstrained paths are paths without any timing constraints specified to them, i.e. set_input_delay, create_clock, etc. The report details the type of unconstrained paths: clocks, input ports, outputs ports.

      Unconstrained endpoints:
      If the endpoint is a sequential cell pin , the clock not reaching the cell and if the endpoint is an output port , the missing output delay.

      both are same without having any timing constraints

  4. What is multidriven net and what is its impact

    1. One driven net is connected to multiple driving nets without using proper logic defined between their interconnections.

  5. what are floating pins and floating ports and floating paths? and what are the difference between them?

  6. Where can we use these ICC commands that you have listed to ensure the checks?