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Saturday, May 16, 2020

Non Linear delay model (NLDM) in VLSI

Timing model in VLSI


1) Linear timing model


2) Nonlinear delay model (NLDM)


Cell Delay (Gate Delay):

Transistors within a gate take a finite time to switch. This means that a change in the input of a gate takes a finite time to cause a change in the output.

Gate delay = f (input transition (slew) time, output load Cnet+Cpin).

Cnet-->Net capacitance

Cpin-->pin capacitance of the driven cell


Timing model:


Cell timing models are used to provide accurate timing for various instances of the cells present in the design. The timing model normally obtained from detailed circuit simulation of the cell to model the actual scenario of the cell operation.


Let’s consider an example of a timing arc of a simple inverter. For the inverter if a rising transition at the input causes a falling transition at the output and vice versa.  So there are two types of delay characterized for the cell first is output rise delay and output fall delay.

Timing Arc delays for an Inverter Cell

These delays are measured based upon the threshold value defined in the library which is typically 50% of the Vdd. Thus delay is measured from input crossing its threshold to the output crossing its threshold.


The delay for the timing arc through the inverter depends on the two factors: The output load i.e. capacitance load at the output and the transition time at the input. The delay value is directly proportional to the load capacitance- larger the load capacitance means larger the delay.


In most cases, the delay increases with increasing input transition time and in some cases the delay through the cell may be showing non-monotonic behavior with respect to the input transition time that means a larger input transition time may produce a smaller delay especially if the output is highly loaded.


The transition time at the output is directly proportional to the output capacitance i.e. output transition time increases with the output load. Thus a large transition time at the input can improve the transition and a slow transition at the input can deteriorate the transition at the output depending upon the cell type and its output load. In the figure shown two cases where the transition time at the output of a cell can improve or deteriorate depending on the load at the output.



Linear timing model:


In this the delay and the output transition time of cells are represented as linear functions of the two-parameter: input transition time and output load capacitance.

The general form of a linear delay model is

D = D0 + D1 * S + D2 * C

Where D0, D1, D2 are constant, S is the input transition time, and C is the output load capacitance.


The linear delay models are not accurate over the range of input transition time and output capacitance for deep submicron technologies so presently most of the cell libraries use the more complex models like Non-linear Delay Model (NLDM) and CCS model.


Non-linear Delay Model (NLDM):


Nowadays the non-linear delay model (NLDM) or the composite current source timing model (CCS) based look-up table (LUT) is widely used for static timing analysis (STA). In those LUTs, the characterization data such as cell delay and transition time is indexed by a fixed number of input transition time and load capacitance values.


A Synopsys Liberty (.lib) format file, also known as a timing library file (Lib file), contains several kinds of LUTs for computing cell delay. Usually, the Lib file is provided by the foundry, however, when a designer wants to have his own cell library or to change some parameters in the process, he needs to generate the lib file himself.


For doing this work, the designer should decide the characteristic parameters input transition time and output load of the LUT and then get the timing information by Hspice simulation or other EDA tools.


After completing the whole library’s characterization, the designer needs to analyze the accuracy of the timing file for the future work by himself, as no EDA tools can analyze it automatically. The accuracy of timing analysis depends on the accuracy of the delay model used in the cell characterization.


The LUT only includes a fixed number of parameters, for example, the size of 5x5 or 7x7 (input transition time and load) pairs, while the delays for the other pairs are obtained using linear interpolation.


As a result, when making a standard cell library of one’s own, choosing appropriate characteristic parameters of input transition time and load is the key work for the accuracy of the timing library file.


NLDM is a highly accurate timing model as it is derived from SPICE characterizations. Most of the cell libraries used table models to specify the delay and timing checks for various timing arcs of the cell, the table model is referred to as an NLDM and are used for calculating the delay, output slew, or other timing checks.


The table gives the delay through the cell for various combinations of input transition time at the cell input pin and total output capacitance at the cell output.An NDLM delay model is represented in two-dimensional form, with two independent variables are the input transition time and the output load capacitance and entries in the table denoting the delay.


Some newer timing libraries also provide advanced timing models based on current sources such as CCS, ECSM, etc. for deep submicron technologies.


Example of delay table for inverter

This is related to rising and falling delay models of inverter timing arc from pin INP1 and OUT as well as max transition allowed time at pin OUT for This separate timing model for the rise and fall delays for output pin and these are denoted as cell_rise and cell_fall respectively.


pin (OUT) {

     max_transition: 1.0;

     timing () {

            related_pin: "INP1";

          timing_sense: negative_unate;

           cell_rise (delay_template_3x3) {

                      index_1 ("0.1, 0.3, 0.7"); /* Input transition */

                      index_2 ("0.16, 0.35, 1.43"); /* Output capacitance */

                      values (/* 0.16 0.35 1.43 */ \

                           /* 0.1 */ "0.0513, 0.1537, 0.5280", \

                          /* 0.3 */ "0.1018, 0.2327, 0.6476", \

                          /* 0.7 */ "0.1334, 0.2973, 0.7252");

}

           cell_fall (delay_template_3x3) {

                     index_1 ("0.1, 0.3, 0.7"); /* Input transition */

                     index_2 ("0.16, 0.35, 1.43"); /* Output capacitance */

                     values ( /* 0.16 0.35 1.43 */ \

                        /* 0.1 */ "0.0617, 0.1537, 0.5280", \

                        /* 0.3 */ "0.0918, 0.2027, 0.5676", \

                        /* 0.7 */ "0.1034, 0.2273, 0.6452");

}


In the lookup table template has two variable is specified, the first variable in the table is the input transition time and the second variable is the output capacitance but this can be in either i.e. the first variable can be output capacitance but usually designer is consistent across all the templates in the library. This form of representing delays in a lookup table is called the Non-Linear delay model because of the nonlinear variations of delay with input transition time and load capacitance.


The NLDM models are not used only for the output delay but also for used for the output transition time which is characterized by the input transition time and the output load. This also separates two-dimensional tables used for computing the output rise and fall transition times of a cell. These are denoted by rise_transition and fall_transition at the output.


pin (OUT) {

    max_transition: 1.0;

     timing () {

             related_pin: "INP";

             timing_sense: negative_unate;

             rise_transition (delay_template_3x3) {

                     index_1 ("0.1, 0.3, 0.7"); /* Input transition */

                     index_2 ("0.16, 0.35, 1.43"); /* Output capacitance */

                     values (/* 0.16 0.35 1.43 */ \

                           /* 0.1 */ "0.0417, 0.1337, 0.4680", \

                           /* 0.3 */ "0.0718, 0.1827, 0.5676", \

                           /* 0.7 */ "0.1034, 0.2173, 0.6452");

                      }

              

              fall_transition (delay_template_3x3) {

                     index_1 ("0.1, 0.3, 0.7"); /* Input transition */

                     index_2 ("0.16, 0.35, 1.43"); /* Output capacitance */

                     values (/* 0.16 0.35 1.43 */ \

                              /* 0.1 */ "0.0817, 0.1937, 0.7280", \

                              /* 0.3 */ "0.1018, 0.2327, 0.7676", \

                              /* 0.7 */ "0.1334, 0.2973, 0.8452");

                              }

                           . . .

                         }

                    . . .

                 }

An inverter cell with a Non-Linear Delay model has the following tables:

Rise delay

Fall delay

Rise transition

Fall transition


Where is that information which specifies that the cell is inverting?

This information is specified in the timing_sense field of the timing arc. For the inverter, the timing arc is negative_unate i.e. the output pin direction is opposite (negative) of the input pin direction. Thus the cell_rise table lookup corresponds to the falling transition time at the input pin and cell_fall table lookup corresponds to the rising transition time at the input pin.


Case1: When Input transition and output load values match with lookup table indexes values.

Based upon the delay table an input fall transition time 0f 0.3ns and an output load of 0.16pf will correspond to the rise delay of the inverter of 0.1018ns because a falling transition at the input gives the inverter output rise.


                     fall_transition (delay_template_3x3) {

                     index_1 ("0.1, 0.3, 0.7"); /* Input transition */

                     index_2 ("0.16, 0.35, 1.43"); /* Output capacitance */

                     values (/* 0.16 0.35 1.43 */ \

                              /* 0.1 */ "0.0817, 0.1937, 0.7280", \

                              /* 0.3 */ "0.1018, 0.2327, 0.7676", \

                              /* 0.7 */ "0.1334, 0.2973, 0.8452");

                        }


Case2: When input transition and output load values doesn't match with table index values

If any port/net on a timing path exceeds a value beyond the LUT’s range, the STA tool extrapolates the desired value from existing LUT tables. However, the linear interpolation method does not guarantee the accuracy of the extrapolated values.


The example is related to where the lookup table does not correspond to any entries available in the table. In this case two-dimensional interpolation is used to provide the resulting delay value. The two nearest values are chosen for the table interpolation in each dimension.


Consider the lookup table for the fall transition for the input transition of 0.14ns and the output capacitance of 1.15pF. The fall transition table given below for two- dimensional interpolation is reproduced below.

                                    

                                   fall_transition (delay_template_3x3)

                                       index1 (“0.1, 0.3 . . .”);

                                     index2 (“. . .  0.35, 1.43”);

                                         values (\

                                             “. . . 0.1937, 07280” \

                                             “. . . 0.2327, 0.7676”

                                               . . . 

Input transition time 0.14ns lies between the 0.1ns and 0.3ns input transition so we assume 0.1ns is x1, 0.3ns is x2 and 0.14ns is x0. Similarly output load 1.15pF lies between the 0.35 and 1.43 output load so we assume 0.35 is y1, 1.43ns is y2 and 1.15 is y0 and corresponding delays entries are T11 = 0.1937, T12=.07280, T21=.2327 and T22=0.7676.


If lookup table is required for (x0, y0), the delay value T00 is obtained by interpolation and the formula is:

X1= 0.1, x2= 0.3 and x0 =0.14

y1= 0.35, y2=1.43 and y0= 1.15

T11 = 0.1937, T12=.7280, T21=.2327 and T22=0.7676.


xo1 = (x0 – x1) / (x2 – x1) = (0.14 – 0.1) / (0.3 – 0.1) = 0.04/0.2 = 0.2

x2o = (x2 – x0) / (x2 – x1) = (0.3 – 0.14) / (0.3 – 0.1) = 0.16/0.2 = 0.8

y01 = (y0 – y1) / (y2 – y1) = (1.15 – 0.35) / (1.43 – 0.35) = 0.8/1.08 =.7407

y20 = (y2 – y0) / (y2 – y1) = (1.43 – 1.15) / (1.43 – 0.35) = .28/1.08 =.3651


T00 = x20 * y20 * T11 + x20 * y01 * T12 + x01 * y20 * T21 + x01 * y01 * T21

Substituting the values

T00 = 0.8 * 0.3651 *0.1937 +0.8 * 0.7407 *.7280 + 0.2 * 0.3651 *.2327 + 0.2 * 0.7407 * 0.7676

         = 0.056575 + 0.43138 + 0.01699 + 0.11371

         = 0.6186


This equation is valid for interpolation as well as extrapolation that means when the indices (x0, y0) lies outside the index1 and index2 (characterized range of indices).


For example, for the lookup table with 0.05 for index1 and 1.7 for index2 then the fall transition value obtained as:

X1= 0.1, x2= 0.3 and x0 =0.05

y1= 0.35, y2=1.43 and y0= 1.7

T11 = 0.1937, T12=.7280, T21=.2327 and T22=0.7676.


xo1 = (x0 – x1) / (x2 – x1) = (0.05 – 0.1) / (0.3 – 0.1) = - 0.05/0.2 = -0.25

x2o = (x2 – x0) / (x2 – x1) = (0.3 – 0.05) / (0.3 – 0.1) = 0.25/0.2 = 1.25

y01 = (y0 – y1) / (y2 – y1) = (1.7 – 0.35) / (1.43 – 0.35) = 1.35/1.08 =1.25

y20 = (y2 – y0) / (y2 – y1) = (1.43 – 1.7) / (1.43 – 0.35) = -0.27/1.08 = -0.25


T00 = x20 * y20 * T11 + x20 * y01 * T12 + x01 * y20 * T21 + x01 * y01 * T21

         =1.25 * (-0.25)* 0.1937 + 1.25 * 1.25 * .7280 + (-0.25) * (-0.25) * 0.2327 + (-0.25) * 1.25 * 0.7676

         = 0.8516


Ques1: How to interpolate and extrapolate delay values from the library?


Ques2: What is standard Cell Characterization Concepts in the library?

It is a process of analyzing a circuit using static and dynamic methods to generate models suitable for chip implementation flows.

No digital chip is possible without cell models. Characterization is necessary for the use of Standard Cells and this is done on extracted netlists.

The Non-linear Delay Model (NLDM) is the most common delay model for the characterization of standard cells.  As we are going to deep sub-micron technology it requires more accurate timing models like CCS (composite current source)

Every digital chip implementation (RTL-to-GDSII) flow requires cell models for analysis (logic simulation, verification, timing, power, noise, etc), implementation (synthesis, test insertion, placement, clock tree synthesis, routing) and fixing (engineering change order, rule fixing, etc).

Ques3: NDLM is related to voltage or current source?

References

1. Static Timing Analysis for Nanometer Designs

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