Wire Load Model (WLM) How do you estimate the parasitics (RC) of a net before placement and routing? Prior to the Routing stage, net paras...
Showing posts with label STA. Show all posts
Showing posts with label STA. Show all posts
Tuesday, May 19, 2020
Saturday, May 16, 2020
Timing model in VLSI 1) Linear timing model 2) Nonlinear delay model (NLDM) Cell Delay (Gate Delay): Transistors within a gate take a ...
Sunday, May 10, 2020
Time Stealing and Time Borrowing Time borrowing: https://www.physicaldesign4u.com/2020/05/time-borrowing-concept-in-sta.html Here s...