Learn physical design concepts in easy way and understand interview related question only for freshers

Saturday, January 11, 2020

Interview questions


sort of question those I faced in my interviews some are from service based company and some are from product based also.....
Interview 1
  1. What are the inputs of Physical design?
  2. What are the content in the .lib, .lef & .tlef files
  3. What are the challenges you faced in your design? If you say congestion, timing, latency then they will ask more question on these challenges.
  4. What is value of Tran, cap, latency and skew in your design?
  5. What are the OCV & AOCV? Why we go for POCV?
  6. What are the commands for multicycle path and generated clock?
  7. How you will confirm that netlist is proper?
  8. How to decide channel width between macros?

Interview 2
  1. What are ECO’s and what are the inputs need for ECO, why we need of it?
  2. What are metal ECO and Base ECO?
  3. What are the inputs of LVS?
  4. What is input and output delay?
  5. What is insertion delay?
  6. What is the clock period in your design and how many levels of clock has been built?

Interview 3
  1. What is DPT layers? How many DPT layers in your design?
  2. Why we are using DPT layers?
  3. What is the difference between FINFET and CMOS? Fin is gate or diffusion?
  4. How fin is connected to metal layers and via?
  5. Consider you have two design design1 with 10k instances and design2 with 1Million instances for both we requires same or different TLU+ files?
  6. What are the effects of crosstalk on setup and hold timing?
  7. How IR drop is affected timing?
  8. IR drop is on power or signal net?
  9. In PNR stage how will you handle the timing issues?
  10. What is the difference between bounds and region?
  11. What are the sanity checks before going for floorplanning?
  12. What is the command for setup violating paths?
  13. What are placement blockages?
  14. What are DRC’s & how will you fix them?


Interview 4
  1. What is NDM?
  2. How much spacing you will give between macros?
  3. What is dynamic power?
  4. Is there any rules to put minimum number of straps between two macros?
  5. What is clock gating and power gating?
  6. What are the low power design techniques?
  7. What are clock routing rules?
  8. What is antenna effect and how will you remove this?

Interview 5
  1. What are Physical design inputs in details?
  2. What SDC files contains?
  3. What is the generated clock and virtual clock?
  4. The timing DRV’s (max Tran, max cap, max fan-out) in the SDC and in the library file are same or different?
  5. What is clock skew and its types?
  6. What is the difference between clock skew and uncertainty?
  7. What SDC contains related to CTS?
  8. What are NDR rules and when we apply these rules?
  9. What is Electro migration and how to reduce it?
  10. What are the guidelines for doing floorplanning? Is there any specific guidelines in 7nm technology for floorplanning?
  11. What is useful skew, local skew and global skew?
  12. What is latency? If you face latency issue in your design what will you do?
  13. What are tap cells and end cap cells?
  14. What problem you faced during placement stages (timing and congestion), how will you tackle these problems?
  15. What are timing DRV’s?
  16. What is HVT, LVT, and ULVT cells?
  17. What are EM and antenna violations and how to fix it?
  18. How to fix Dynamic IR drop?
  19. How to fix setup violations?
  20. Can single path have both setup and hold violation? If yes why and if no why?
  21. In OCV how to derate the values?
  22. What are clock synchronizers why we used them?
  23. What are standard cells and how to improve the delay of standard cells?
  24. What is path delay, on what factor it is depends?
  25. What is the difference between crosstalk delay and crosstalk noise?
  26. What are the guidelines for floorplanning?
  27. How to find the setup for flip-flop? On what factors setup is depend?


Interview 6
  1. Why shielding we used?
  2. What are Blockage creation command?
  3. Fence region and bound difference?
  4. What is command to show only all setup violating paths?
  5. If clock is not reaching to particular flops how will you report it?
  6. What are the number of clocks in your design and how you balance the skew?
  7. How to reduce dynamic power?
  8. What is Static and dynamic power and what are the sources of these powers in CMOS and how to reduce?
  9. In CMOS if you are changes the place of PMOS and NMOS with each other what will happen and why?
  10. What is the difference between ASIC and FPGA?

Interview 7
  1. What are the inputs for synthesis?
  2. How you resolved timing violations in your design?
  3. How many metal layers are present in your design? On what basis the metals are divided?
  4. What is the flow for physical design, explain each part?
  5. What types of DRC’s you saw in the design and how did you resolve?
  6. In library file how particular cell is defined stepwise?
  7. Why setup and hold violates in same path? Give reasons.
  8. What is the skew if more positive skew which is violate (setup/hold)?
  9. In latency what is the root buffer? Why we consider the latency? What is the use of this?
  10. What is LVS, where do you fix LVS & how many types of LVS issues are there in the design and how you fixed?

Interview 8
  1. What are the contents in UPF?
  2. There is a reg to reg path in that setup is violating then how to fix setup if you already applied all the techniques?
  3. What is isolation cells, if we are not using this what will happened?
  4. What is multibit banking and need of it?
  5. What are the STA inputs, explain each?
  6. What contains in SDC?
  7. What is the frequency and time period of your design?
  8. How many paths have you seen in your design and types of those paths?
  9. What is CRPR and how it work in STA?
  10. What is OCV analysis, how to give derate values to the paths?
  11. Tell me about your design is power aware or not?
  12. What is clock Tran and data Tran and how to fix these violation?
  13. In routing stage what are the issues you faced?
  14. What is pulse width violation if it is in design how to reduce?
  15. What is difference between clock buffer and normal buffer?

Interview 9
  1. Have you seen any End cap cells around the macros if yes why we are using them?
  2. What information are presents in DEF. In DEF there are special nets what is the use of them?
  3. What is Eletromigration?
  4. What is antenna effect?
  5. What type of DRC you seen in your design and how to fix them?
  6. Have you checked DRC in ICC2 or only in caliber?
  7. What are the NDR rules you follow in your design?
  8. How power planning is done?
  9. If two tap cells are overlapped what kind of DRC issue will be there?
  10. Can we overlap the Macros with Tap cells?
  11. Why end cap are present in the design?
  12. On what factors you will decide distance between two macros?
  13. On what basis you placed your macros in core area?
  14. What is the flow of your project?
  15. If congestion is not reduced by doing all techniques what will you do?
  16. Consider two scenario like if you are reducing congestion timing is worst and if you are doing on timing is good but now congestion is worst then what should you do for that?
  17. Why we are using NDR rules?


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4 comments:

  1. If two tap cells are overlapped what kind of DRC issue will be there?

    ReplyDelete
    Replies
    1. base DRC violations (below metal 0 like poly n diffusion related) , latchup issues

      Delete
  2. If any two cells overlap we will face huge violations in base drc violations like poly diffusion fti violations etc

    ReplyDelete
  3. hi madam, colud you please provide answers for all above questions that will be helpful to prepare for an interview.

    ReplyDelete