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Wednesday, March 3, 2021

AMD interview Questions (Physical Design)

 AMD interview Questions (Physical Design)

  1. Tell me about your experience.
  2. How will you make sure that your power structure is good?
  3. Tell me about DRC and LVS fixes.
  4. Why we are following certain guidelines for macros placement and what are those guidelines?
  5. What is the minimum space required in between macros if the channel is there on the non-pin side of macros?
  6. What is the distance between tap cells in your design?
  7. What are the setup and hold edges for a 3-level multi-cycle path?
  8. What are the setup and hold edges for the half-cycle path?
  9. How you will perform cell spreading in placement if congestion is there?
  10. Tell me about the 2-pass approach in placement.
  11. Why we are not taking care of hold violations at the placement stage?
  12. Tell me about multi-source CTS.
  13. Tell me about Switching power, internal power, average power, peak power, and IR Drop.
  14. Tell me about CPPR.
  15. What are the differences between OCV and POCV?
  16. What are the setup and hold edges for the half-cycle path?
  17. What are the setup and hold edges for the positive latch to negative flop?
  18. Tell me about setup and hold violation fixes which are occurred in the same path.`
  19. How will you apply to derate?
  20. Tell me about DPT.
  21. Tell me about X-talk delta and X-talk noise.
  22. What are the different ways to fix setup and hold? Which one is difficult to fix setup? or hold?
  23. Which violation you will fix first? Is it set up or hold?
  24. Tell me about scan-chain reordering.
  25. What are the timing arcs for flipflop when we have scan-chain reordering?
  26. How will you improve your insertion delay? 
  27. And some other timing-related scenarios w.r.t. setup and hold fixes.
  28. Explain sanity checks.
  29. What check_design will report?
  30. What is the issue, if inputs are floating?
  31. Is there any issue in the case of outputs floating?
  32. What check_timing will report?
  33. What check_library will report?
  34. On what basis, macros will be keeping inside the design?
  35. What is the use of keep-out margin around the macros?
  36. Is it compulsory to keep out margin around macros?
  37. Explain the order of keeping preplace cells?
  38. Tap cells information will be in which file?
  39. On what basis, the distance between tap cells will be decided?
  40. Format of keeping tap cells inside the core area.
  41. How many std cells are being accommodated by each tap cell.
  42. What is the use of keeping tap cells in checkerboard format rather than keeping continuous?
  43. What is the purpose of endcap cells?
  44. Why can’t we keep endcaps on the top and bottom of macros?
  45. What is isolation cell, retentions cell?
  46. What are the checks after the floorplan?
  47. How the tool will place std cells in the design.
  48. How to fix congestion?
  49. Prioritize timing DRCs, timing, DRC.
  50. What is the purpose of IO buffers?
  51. Among Max Trans, Max cap, Max fanout.....which one will be fixed first.
  52. Difference between normal buffers and clock buffers.
  53. Checks after placement.
  54. What are the contents of the clock spec file?
  55. What is NDR?
  56. When we will enable NDR.
  57. What are the inputs to PT?


  1. hi will u please provide answer for these questions...that will be very much helpfull,i like u r blog very muchhhh....thank you

  2. you are doing wonderful job please continue like this with other companies interviews like intel, nvidia, samsung, mediatek.
    please post those questions too...

  3. Could you please share answers as well.